WORKSHOP PAPER
Highlight Scene FPN on Shared Pixels and a Reduction Technique
Abstract
Shared pixel technology is most common in recent small pixel CMOS image sensors. In the case of vertically shared pixels, it has been observed horizontal line FPN with the period of shared pixels when highlight scene is imaged and integration period is reduced to very short time by electronic shuttering. The reason for the phenomena and the technique for reducing it are presented, with the results showing the FPN reduced to below background level.Keywords
Shared pixel technology, CMOS image sensors, FPN reduction,References
1) R.D.McGrath, et al., "Shared pixels for CMOS image sensor arrays", Proceeding of 2005 IEEE Workshop on CCD and AIS
2) H.Takahashi et al., "A 3.9um pixel pitch VGA format 10b digital sensor with 1.5-transistor/pixel", ISSCC Dig. Tech. Papers. https://doi.org/10.1109/isscc.2004.1332617
3) S.Yoshihara, et al., "A 1/1.8-inch 6.4 M pixel 60 frame/s CMOS image sensor with seamless mode change", ISSCC Dig. Tech. Papers. https://doi.org/10.1109/isscc.2006.1696257
4) J.Kim, et al., "1/2.5' 8 mega-pixel CMOS image sensor with enhanced image quality for DSC application", IEDM Proc.. https://doi.org/10.1109/iedm.2006.346975
5) M.Mori, et al., "A 1/4in 2M pixel CMOS image sensor with 1.75 transistor/pixel", ISSCC Dig. Tech. Papers. https://doi.org/10.1109/isscc.2004.1332618
6) M.Cohen, et al., "Fully optimized Cu based process with dedicated cavity etch for 1.75um and 1.45um pixel pitch CMOS image sensors", IEDM Proc.. https://doi.org/10.1109/iedm.2006.346976
7) K-B.Cho, et al., "A 1/2.5 inch 8.1M pixel CMOS image sensor for digital cameras", ISSCC Dig. Tech. Papers
8) L.J.Kozlowski, et al., "Performance limits in visible and infrared image sensors", IEDM Proc.. https://doi.org/10.1109/iedm.1999.824286