Switching Sequence Control 31-Level Asymmetric Cascaded of Reduced Switch Count Multilevel Inverter with Multi Carrier Pulse Width Modulation

Abstract

Various pulse width modulation techniques, including as cascaded multilevel inverters (MLI), diode clamped multilevel inverters, and flying capacitor multilevel inverters, can be used to simply operate common inverters. Due to increased switching losses, current MLIs cannot reach high efficiency. Due to lower losses and THD than standard MLI topologies, the asymmetric cascaded multi-level H-bridge inverter architecture examined in this white paper employs fewer switches and more output voltage levels (Total Harmonic Distortion). The THD is less than the IEEE standard because of the suggested architecture. In this instance, phase difference (PD) multi-carrier PWM techniques are used to control the gate pulses using sinusoidal reference. Each switch receives a different pulse pattern thanks to a method of decimal-to-binary conversion. It is possible to utilise the suggested circuit for applications requiring moderate to high power, and it is quite simple to evaluate. Utilize the MATLAB/SIMULINK environment to simulate time-domain behaviour for the 31-level and 33-level multilevel inverter topologies.