Quasi Isolation QoS Setups to Control MPSoC Contention in Integrated Software Architectures

Authors Sergio Garcia-Esteban , Alejandro Serrano-Cases , Jaume Abella , Enrico Mezzetti , Francisco J. Cazorla



PDF
Thumbnail PDF

File

LIPIcs.ECRTS.2023.5.pdf
  • Filesize: 1.23 MB
  • 25 pages

Document Identifiers

Author Details

Sergio Garcia-Esteban
  • Polytechnic University of Catalonia, Barcelona, Spain
  • Barcelona Supercomputing Center (BSC), Spain
Alejandro Serrano-Cases
  • Barcelona Supercomputing Center (BSC), Spain
  • Rapita Systems S.L., Barcelona, Spain
Jaume Abella
  • Barcelona Supercomputing Center (BSC), Spain
Enrico Mezzetti
  • Barcelona Supercomputing Center (BSC), Spain
  • Rapita Systems S.L., Barcelona, Spain
Francisco J. Cazorla
  • Barcelona Supercomputing Center (BSC), Spain
  • Rapita Systems S.L., Barcelona, Spain

Cite AsGet BibTex

Sergio Garcia-Esteban, Alejandro Serrano-Cases, Jaume Abella, Enrico Mezzetti, and Francisco J. Cazorla. Quasi Isolation QoS Setups to Control MPSoC Contention in Integrated Software Architectures. In 35th Euromicro Conference on Real-Time Systems (ECRTS 2023). Leibniz International Proceedings in Informatics (LIPIcs), Volume 262, pp. 5:1-5:25, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)
https://doi.org/10.4230/LIPIcs.ECRTS.2023.5

Abstract

The use of integrated architectures, such as integrated modular avionics (IMA) in avionics, IMA-SP in space, and AUTOSAR in automotive, running on Multi-Processor System-on-Chip (MPSoC) is on the rise. Timing isolation among the different software partitions or applications thereof in an integrated architecture is key to simplifying software integration and its timing validation by ensuring the performance of each partition has no or very limited impact on others despite they share MPSoC’s hardware resources. In this work, we contend that the increasing hardware support for Quality of Service (QoS) guarantees in modern MPSoCs can be leveraged via specific setups to provide strong, albeit not full, isolation among different software partitions. We introduce the concept of Quasi Isolation QoS (QIQoS) setups and instantiate it in the Xilinx Zynq UltraScale+. To that end, out of the millions of setups offered by the different QoS mechanisms, we identify specific QoS configurations that isolate the traffic of time-critical software partitions executing in the core cluster from that generated by contender partitions in the programmable logic. Our results show that the selected isolation setup results in performance variations of the partitions run in the computing cores that are below 6 percentage points, even under scenarios with extremely high traffic coming from the programmable logic.

Subject Classification

ACM Subject Classification
  • Computer systems organization → Real-time system architecture
Keywords
  • Multicore
  • Interference
  • QoS

Metrics

  • Access Statistics
  • Total Accesses (updated on a weekly basis)
    0
    PDF Downloads

References

  1. Irune Agirre, Jaume Abella, Mikel Azkarate-askasua, and Francisco J. Cazorla. On the tailoring of CAST-32A certification guidance to real COTS multicore architectures. In 12th IEEE International Symposium on Industrial Embedded Systems, SIES, Toulouse, France, June 14-16, 2017, pages 1-8. IEEE, 2017. URL: https://doi.org/10.1109/SIES.2017.7993376.
  2. ApolloAuto. Apollo 3.0 Software Architecture, 2018. URL: https://github.com/ApolloAuto/apollo/blob/master/docs/specs/Apollo_3.0_Software_Architecture.md.
  3. ApolloAuto. Perception, 2018. URL: https://github.com/ApolloAuto/apollo/blob/r3.0.0/docs/specs/perception_apollo_3.0.md.
  4. ARINC Inc. ARINC Specification 653: Avionics Application Software Standard Standard Interface, June 2012. Google Scholar
  5. Arm. ARM CoreLink NIC-400 Network Interconnect Technical Reference Manual. Google Scholar
  6. Arm. ARM CoreLink QoS-400 Network Interconnect Advanced Quality of Service Supplement to ARM CoreLink NIC-400 Network Interconnect Technical Reference Manual, 2017. Google Scholar
  7. Arm. ARM CoreLink QVN-400 Network Interconnect Advanced Quality of Service using Virtual Networks Supplement to ARM CoreLink NIC-400 Network Interconnect Technical Reference Manual, 2017. Google Scholar
  8. Arm. ARM Cortex-A53 MPCore Processor Technical Reference Manual. Version r0p4, 2022. URL: https://developer.arm.com/documentation/ddi0500/j/.
  9. Arm. Arm® Architecture Reference Manual Supplement Memory System Resource Partitioning and Monitoring (MPAM), for Armv8-A, 2022. Google Scholar
  10. Arm. Cortex-R5 and Cortex-R5F Technical Reference Manual. Version r1p1, 2022. URL: https://developer.arm.com/documentation/ddi0460/c/.
  11. Arm. Mali-400, 2022. URL: https://developer.arm.com/Processors/Mali-400.
  12. ARP4761. Guidelines and Methods for Conducting the Safety Assessment Process on Civil Airborne Systems and Equipment, 2001. Google Scholar
  13. AUTOSAR. Technical Overview V2.0.1, 2006. Google Scholar
  14. Jingyi Bin, Sylvain Girbal, Daniel Gracia Pérez, Arnaud Grasset, and Alain Mérigot. Studying co-running avionic real-time applications on multi-core COTS architectures. In Embedded Real Time Software and Systems (ERTS2014), 2014. URL: https://hal.science/hal-02271379.
  15. Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Chen-Yong Cher, and Mateo Valero. Software-Controlled Priority Characterization of POWER5 Processor. In 35th International Symposium on Computer Architecture (ISCA), pages 415-426, 2008. URL: https://doi.org/10.1109/ISCA.2008.8.
  16. Marco Caccamo, Rodolfo Pellizzoni, Lui Sha, Gang Yao, and Heechul Yun. MemGuard: Memory Bandwidth Reservation System for Efficient Performance Isolation in Multi-Core Platforms. In 2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS), pages 55-64, USA, April 2013. IEEE Computer Society. URL: https://doi.org/10.1109/RTAS.2013.6531079.
  17. Jordi Cardona, Carles Hernandez, Enrico Mezzetti, Jaume Abella, and Francisco J. Cazorla. NoCo: ILP-based worst-case contention estimation for mesh real-time manycores. In 2018 IEEE Real-Time Systems Symposium (RTSS). IEEE, December 2018. URL: https://doi.org/10.1109/rtss.2018.00043.
  18. Certification Authorities Software Team. CAST-32A Multi-core Processors, 2016. Google Scholar
  19. Dakshina Dasari and Vincent Nelis. An analysis of the impact of bus contention on the WCET in multicores. In HPCC, 2012. URL: https://doi.org/10.1109/HPCC.2012.212.
  20. DDC-I. Deos, a Time and Space Partitioned, Multi-core Enabled, RTOS Verified to DO-178C ED-12C DAL A, 2022. URL: https://www.ddci.com/products_deos_do_178c_arinc_653/.
  21. EASA, FAE. General Acceptable Means of Compliance for Airworthiness of Products, Parts and Appliances (AMC-20). Amendment 23. Annex I to ED Decision 2022/001/R. AMC 20-193 Use of multi-core processors., 2022. URL: https://www.easa.europa.eu/en/document-library/certification-specifications/amc-20-amendment-23.
  22. Falk Rehm and Jörg Seitter. Software Mechanisms for Controlling QoS. In 2021 Design, Automation & Test in Europe Conference & Exhibition, DATE 2021, Virtual Conference, February 01-05, 2021, pages 1485-1488, 2016. Google Scholar
  23. Fernando Fernandes dos Santos, Lucas Draghetti, Lucas Weigel, Luigi Carro, Philippe Navaux, and Paolo Rech. Evaluation and Mitigation of Soft-Errors in Neural Network-Based Object Detection in Three GPU Architectures. In 47th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W), pages 169-176, 2017. URL: https://doi.org/10.1109/DSN-W.2017.47.
  24. Gabriel Fernandez, Javier Jalle, Jaume Abella, Eduardo Quiñones, Tullio Vardanega, and Francisco J. Cazorla. Resource usage templates and signatures for COTS multicore processors. In Proceedings of the 52nd Annual Design Automation Conference, San Francisco, CA, USA, June 7-11, 2015, pages 155:1-155:6. ACM, 2015. URL: https://doi.org/10.1145/2744769.2744901.
  25. Javier Fernández, Jon Perez, Irune Agirre, Imanol Allende, Jaume Abella, and Francisco J. Cazorla. Towards functional safety compliance of matrix–matrix multiplication for machine learning-based autonomous systems. Journal of Systems Architecture, 121:102298, 2021. URL: https://doi.org/10.1016/j.sysarc.2021.102298.
  26. Freescale semicondutor. QorIQ T2080 Reference Manual, 2016. Also supports T2081. Doc. No.: T2080RM. Rev. 3, 11/2016. Google Scholar
  27. Jonah Gamba. Automotive radar applications. In Radar Signal Processing for Autonomous Driving, pages 123-142. Springer Singapore, Singapore, 2020. URL: https://doi.org/10.1007/978-981-13-9193-4_9.
  28. Giovani Gracioli, Ahmed Alhammad, Renato Mancuso, Antônio Augusto Fröhlich, and Rodolfo Pellizzoni. A Survey on Cache Management Mechanisms for Real-Time Embedded Systems. ACM Computing Surveys, 48(2):32:1-32:36, November 2015. URL: https://doi.org/10.1145/2830555.
  29. Giovani Gracioli, Rohan Tabish, Renato Mancuso, Reza Mirosanlou, Rodolfo Pellizzoni, and Marco Caccamo. Designing Mixed Criticality Applications on Modern Heterogeneous MPSoC Platforms. In Sophie Quinton, editor, 31st Euromicro Conference on Real-Time Systems (ECRTS 2019), volume 133, pages 27:1-27:25, Dagstuhl, Germany, 2019. Schloss Dagstuhl-Leibniz-Zentrum fuer Informatik. URL: https://doi.org/10.4230/LIPIcs.ECRTS.2019.27.
  30. Danlu Guo, Mohamed Hassan, Rodolfo Pellizzoni, and Hiren Patel. A Comparative Study of Predictable DRAM Controllers. ACM Trans. Embed. Comput. Syst., 17(2), February 2018. URL: https://doi.org/10.1145/3158208.
  31. Andrew Herdrich, Ramesh Illikkal, Ravi Iyer, Ronak Singhal, Matt Merten, and Martin Dixon. SMT QoS: Hardware Prototyping of Thread-level Performance Differentiation Mechanisms. In USENIX Workshop on Hot Topics in Parallelism, Berkeley, CA, 2012. USENIX Association. Google Scholar
  32. Denis Hoornaert, Shahin Roozkhosh, and Renato Mancuso. A Memory Scheduling Infrastructure for Multi-Core Systems with Re-Programmable Logic. In Björn B. Brandenburg, editor, 33rd Euromicro Conference on Real-Time Systems (ECRTS 2021), volume 196, pages 2:1-2:22, Dagstuhl, Germany, 2021. Schloss Dagstuhl - Leibniz-Zentrum für Informatik. URL: https://doi.org/10.4230/LIPIcs.ECRTS.2021.2.
  33. Intel. Intel® Resource Director Technology (Intel® RDT) on 2nd Generation Intel® Xeon® Scalable Processors Reference Manual, Rev. 1.0, 2019. Google Scholar
  34. International Organization for Standardization. ISO/DIS 26262. Road Vehicles - Functional Safety, 2009. Google Scholar
  35. Dan Iorga, Tyler Sorensen, John Wickerson, and Alastair F. Donaldson. Slow and Steady: Measuring and Tuning Multicore Interference. In 26th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'20), pages 200-212, April 2020. URL: https://doi.org/10.1109/RTAS48715.2020.000-6.
  36. Javier Jalle, Mikel Fernandez, Jaume Abella, Jan Andersson, Mathieu Patte, Luca Fossati, Marco Zulianello, and Francisco J. Cazorla. Bounding Resource-Contention Interference in the Next-Generation Multipurpose Processor (NGMP). In 8th European Congress on Embedded Real Time Software and Systems (ERTS 2016), 2016. URL: https://hal.science/hal-01259133.
  37. Javier Jalle, Eduardo Quiñones, Jaume Abella, Luca Fossati, Marco Zulianello, and Francisco J. Cazorla. A Dual-Criticality Memory Controller (DCmc): Proposal and Evaluation of a Space Case Study. In RTSS, pages 207-217. IEEE Computer Society, 2014. URL: https://doi.org/10.1109/RTSS.2014.23.
  38. Matthias Jung, Sally A. McKee, Chirag Sudarshan, Christoph Dropmann, Christian Weis, and Norbert Wehn. Driving into the memory wall: the role of memory for advanced driver assistance systems and autonomous driving. In Bruce Jacob, editor, Proceedings of the International Symposium on Memory Systems, MEMSYS. ACM, 2018. URL: https://doi.org/10.1145/3240302.3240322.
  39. Hyoseung Kim, Dionisio De Niz, Björn Andersson, Mark Klein, Onur Mutlu, and Ragunathan Rajkumar. Bounding and Reducing Memory Interference in COTS-Based Multi-Core Systems. Real-Time Syst., 52(3):356-395, May 2016. URL: https://doi.org/10.1007/s11241-016-9248-1.
  40. LYNX Sofware technologies. LynxSecure Separation Kernel Hypervisor, 2022. URL: https://www.lynx.com/products/lynxsecure-separation-kernel-hypervisor.
  41. Kristiyan Manev, Anuj Vaishnav, and Dirk Koch. Unexpected Diversity: Quantitative Memory Analysis for Zynq UltraScale+ Systems. In 2019 International Conference on Field-Programmable Technology, pages 179-187, 2019. URL: https://doi.org/10.1109/ICFPT47387.2019.00029.
  42. Reza Mirosanlou, Mohamed Hassan, and Rodolfo Pellizzoni. Duetto: Latency Guarantees at Minimal Performance Cost. In 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), pages 1136-1141, 2021. URL: https://doi.org/10.23919/DATE51398.2021.9474062.
  43. Jan Nowotsch, Michael Paulitsch, Daniel Buhler, Henrik Theiling, Simon Wegener, and Michael Schmidt. Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement. In 26th Euromicro Conference on Real-Time Systems, ECRTS, 2014. URL: https://doi.org/10.1109/ECRTS.2014.20.
  44. NXP Semiconductors. QorIQ LX2160A Reference Manual, 2021. Supports LX2120A and LX2080A. Google Scholar
  45. Xavier Palomo, Enrico Mezzetti, Jaume Abella, Reinder J. Bril, and Francisco J. Cazorla. Accurate ILP-Based Contention Modeling on Statically Scheduled Multicore Systems. In IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pages 15-28. IEEE, 2019. URL: https://doi.org/10.1109/RTAS.2019.00010.
  46. Jon Pérez-Cerrolaza, Roman Obermaisser, Jaume Abella, Francisco J. Cazorla, Kim Grüttner, Irune Agirre, Hamidreza Ahmadian, and Imanol Allende. Multi-core Devices for Safety-critical Systems: A Survey. ACM Comput. Surv., 53(4), 2020. Google Scholar
  47. RTCA and EUROCAE. DO-178C - ED-12C, Software Considerations in Airborne Systems and Equipment Certification, 2011. Google Scholar
  48. Alejandro Serrano-Cases, Juan M. Reina, Jaume Abella, Enrico Mezzetti, and Francisco J. Cazorla. Leveraging Hardware QoS to Control Contention in the Xilinx Zynq UltraScale+ MPSoC. In 33rd Euromicro Conference on Real-Time Systems, ECRTS 2021, July 5-9, 2021, Virtual Conference, volume 196, pages 3:1-3:26. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2021. URL: https://doi.org/10.4230/LIPIcs.ECRTS.2021.3.
  49. Parul Sohal, Michael Bechtel, Renato Mancuso, Heechul Yun, and Orran Krieger. A Closer Look at Intel Resource Director Technology (RDT). In Proceedings of the 30th International Conference on Real-Time Networks and Systems, pages 127-139, New York, NY, USA, 2022. Association for Computing Machinery. URL: https://doi.org/10.1145/3534879.3534882.
  50. Parul Sohal, Rohan Tabish, Ulrich Drepper, and Renato Mancuso. Profile-driven memory bandwidth management for accelerators and CPUs in QoS-enabled platforms. Real Time Syst., 58(3):235-274, 2022. Google Scholar
  51. Synopsys. Synopsys Enhanced Universal DDR Memory Controller (uMCTL2). URL: https://www.synopsys.com/dw/ipdir.php?ds=dwc_ddr_universal_umctl2.
  52. Hamid Tabani, Roger Pujol, Jaume Abella, and Francisco J. Cazorla. A Cross-Layer Review of Deep Learning Frameworks to Ease Their Optimization and Reuse. In IEEE 23rd International Symposium on Real-Time Distributed Computing (ISORC), 2020. URL: https://doi.org/10.1109/ISORC49007.2020.00030.
  53. Lee Teschler. The basics of automotive radar, 2019. URL: https://www.designworldonline.com/the-basics-of-automotive-radar/.
  54. P. Valsan and H. Yun. MEDUSA: A Predictable and High-Performance DRAM Controller for Multicore Based Embedded Systems. In 2015 IEEE 3rd International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA), pages 86-93, Los Alamitos, CA, USA, August 2015. IEEE Computer Society. URL: https://doi.org/10.1109/CPSNA.2015.24.
  55. Prathap Kumar Valsan, Heechul Yun, and Farzad Farshchi. Taming Non-Blocking Caches to Improve Isolation in Multicore Real-Time Systems. In IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), Vienna, Austria, April 11-14, 2016. URL: https://doi.org/10.1109/RTAS.2016.7461361.
  56. James Windsor, Marie-Hélène Deredempt, and Regis De-Ferluc. Integrated modular avionics for spacecraft — User requirements, architecture and role definition. In IEEE/AIAA 30th Digital Avionics Systems Conference, 2011. URL: https://doi.org/10.1109/DASC.2011.6096141.
  57. Xi-Yue Xiang, Saugata Ghose, Onur Mutlu, and Nian-Feng Tzeng. A model for Application Slowdown Estimation in on-chip networks and its use for improving system fairness and performance. In 34th IEEE International Conference on Computer Design, ICCD, Scottsdale, AZ, USA, pages 456-463. IEEE Computer Society, 2016. URL: https://doi.org/10.1109/ICCD.2016.7753327.
  58. XILINX. Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit. URL: https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html#information.
  59. XILINX. Rockwell Collins Uses Zynq UltraScale+ RFSoC Devices in Revolutionizing How Arrays are Produced and Fielded: Powered by Xilinx, 2018. URL: https://www.xilinx.com/video/corporate/rockwell-collins-rfsoc-revolutionizing-how-arrays-are-produced.html.
  60. XILINX. Zynq UltraScale+ Device. Technical Reference Manual. UG1085 (v2.1), 2019. Google Scholar
  61. XILINX. LogiCore AXI Traffic Generator. https://www.xilinx.com/products/intellectual-property/axi_tg.html, 2022.
  62. XILINX. XILINX VERSAL. AI EDGE. https://www.xilinx.com/products/silicon-devices/acap/versal.html, 2022.
  63. Matteo Zini, Daniel Casini, and Alessandro Biondi. Analyzing Arm’s MPAM From the Perspective of Time Predictability. IEEE Transactions on Computers, 72(1):168-182, 2023. URL: https://doi.org/10.1109/TC.2022.3202720.
  64. Matteo Zini, Giorgiomaria Cicero, Daniel Casini, and Alessandro Biondi. Profiling and controlling I/O-related memory contention in COTS heterogeneous platforms. Software: Practice and Experience, 52(5):1095-1113, 2022. URL: https://doi.org/10.1002/spe.3053.
Questions / Remarks / Feedback
X

Feedback for Dagstuhl Publishing


Thanks for your feedback!

Feedback submitted

Could not send message

Please try again later or send an E-mail