Performance Improvement of Trench-Gate SiC MOSFETs by Localized High-Concentration N-Type Ion Implantation

Rina Tanaka; Katsutoshi Sugawara; Yutaka Fukui; Hideyuki Hatta; Hidenori Koketsu; Hiroyoshi Suzuki; Yusuke Miyata; Kensuke Taguchi; Yasuhiro Kagawa; Shingo Tomohisa; Naruhisa Miura

doi:10.4028/www.scientific.net/MSF.1004.770

Paper Titles

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The IMOSFET: A Deeply-Scaled Fully-Self-Aligned Trench MOSFET
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Challenges in Extremely Low Specific On-Resistance with SiC SJ-VMOSFETs
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Effects of Grounding Bottom Oxide Protection Layer in Trench-Gate SiC-MOSFET by Tilted Al Implantation
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Performance Improvement of Trench-Gate SiC MOSFETs by Localized High-Concentration N-Type Ion Implantation
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1200 V / 200 A V-Groove Trench MOSFET Optimized for Low Power Loss and High Reliability
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Demonstration of Superior Static, Dynamic, and Short-Circuit Performance of 1.2 kV 4H-SiC Split-Gate Octagonal Cell MOSFETs Compared with Linear, Square, and Hexagonal Topologies
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Experimental Study of Switching and Short-Circuit Performance of 1.2 kV 4H-SiC Accumulation and Inversion Channel Power MOSFETs
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Highly Efficient Switching Operation of 1.2 kV-Class SiC SWITCH-MOS
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Performance Improvement of Trench-Gate SiC MOSFETs by Localized High-Concentration N-Type Ion Implantation

Abstract:

Gate oxide reliability of a trench-gate SiC MOSFET can be improved by incorporating a gate protection structure, but the resulting parasitic JFET resistance is one major drawback. For reduction of on-resistance, a new method of localized high-concentration n-type doping in JFET regions (JD) is developed. Utilizing process and device simulation by TCAD, the optimal condition of JD that enables maximum device performance is derived. By fabricating a device with the optimal JD structure, the on-resistance is successfully reduced by 25% compared to a conventional device without JD, while maintaining the withstand voltage and the gate oxide electric field at the same level. As a result, a device exhibiting a specific on-resistance of 1.84 mΩcm² and a breakdown voltage of 1560 V is obtained. The optimal JD structure maintains the short-circuit safe operation area comparable to that for the structure without JD. Thus, by reducing the JFET resistance while minimizing effects on other characteristics, localized JD is shown to be an effective means of realizing a reliable, low-resistance SiC power device.