Model to Plan and Control the Generational Transition of DRAM Industry

Ying Mei Tu; Tun Hao Hsu

doi:10.4028/www.scientific.net/AMR.694-697.3458

Paper Titles

A Study of the Material Re-Issued Models for an Insufficient Output of the LED Chip Manufacturing Plant
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An Integrated Purchase and Production Model for Solar Manufacturing
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An Order Fulfillment Model for the LED Chip Manufacturing Plant
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Model to Evaluate Production Performance of Twin-Fab under Capacity Support
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Model to Plan and Control the Generational Transition of DRAM Industry
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Research on Emergency Supplies Scheduling Problem with Robust Optimization Approach
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Research on Supply Chain Profit Coordination Mechanism Based on JIT Lot-Splitting
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Selecting Candidate Suppliers Using a Multiple Criteria Decision Making Model
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Study on Pricing Method for New Technology Products of Infrastructure Engineering Field
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HomeAdvanced Materials ResearchAdvanced Materials Research Vols. 694-697Model to Plan and Control the Generational...

Model to Plan and Control the Generational Transition of DRAM Industry

Abstract:

DRAM industry is not only among the largest manufacturing industries in the world, but also the most competitive. Furthermore, due to DRAM business is characterized by short life cycles, along with highly competition, the manufacturers are forced to migrate to advanced technology quickly. Under this circumstance, the manufacturers have to launch new technology and purchase generational equipment to meet the market demand and reduce manufacturing cost frequently. This paper investigates the technology generational transition of DRAM industry from manufacturing and planning perspectives. The concept of TOC is applied to schedule the production plan of the new/old products. Regarding to shop floor control, three definitions of cycle time are used to diagnose the production status. Finally, the workload ratio of bottleneck is used for the release decision to adjust the rhythm of production.

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Periodical:

Advanced Materials Research (Volumes 694-697)

Pages:

3458-3461

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.694-697.3458

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Online since:

May 2013

Authors:

Ying Mei Tu, Tun Hao Hsu

Keywords:

DRAM, Generational Transition, TOC, Workload Ratio

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References

[1] J. Hastings: AmCoEx Five Year Comparison of Used Computer Prices, Computer Currents, 9, (1994), pp.20-24.

Google Scholar

[2] Y. Iwata, K. Taji, and H. Tamura: Multi-objective capacity planning for agile semiconductor manufacturing, Production Planning & Control, 14(3), (2003), pp.244-254.

DOI: 10.1080/09537280310000102586

Google Scholar

[3] A. K. Walid, and A. Gharbi: Capacity estimation of a multi-product unreliable production line, International Journal of Production Research, 40(18), (2002), pp.4815-4834.

DOI: 10.1080/0020754021000024148

Google Scholar

[4] C. R. Glassey, and M. G. C. Resende: A scheduling rule for job shop release in semiconductor fabrication, Operations Research Letters 7/5, (1988), pp.213-217.

DOI: 10.1016/0167-6377(88)90033-8

Google Scholar

[5] L. M. Wein: Scheduling semiconductor wafer fabrication, IEEE Transactions on Semiconductor Manufacturing, 1(3), (1988), pp.115-130.

DOI: 10.1109/66.4384

Google Scholar

[6] M. L. Spearman, D. L. Woodruff, and W. J. Hopp: CONWIP: a pull alternative to kanban, International Journal of Production Research, 28(5), (1989), pp.879-894.

DOI: 10.1080/00207549008942761

Google Scholar

[7] R. M. Dabbas and J. W. Fowler: A new scheduling approach using combined dispatching criteria in wafer fabs. IEEE Transactionson Semiconductor Manufacturing, 16(3), (2003), pp.501-510.

DOI: 10.1109/tsm.2003.815201

Google Scholar

[8] Y. H. Lee, and J. W. Kim: Daily stepper scheduling rule in the semiconductor manufacturing for MTO products, International Journal of Advanced Manufacturing Technology, (54), (2011), pp.323-336.

DOI: 10.1007/s00170-010-2934-6

Google Scholar

[9] D. Meyersdorf and T. Yang: Cycle time reduction for semiconductor wafer fabrication facilities, Advanced Semiconductor Manufacturing Conference and Workshop, 1997. IEEE/SEMI , vol. 10, no.12, (1997), pp.418-423.

DOI: 10.1109/asmc.1997.630772

Google Scholar