Dual-Core FFT Processor Based on a High-Speed Real-Time Floating-Point Butterfly Processing Element

Jun Yang; Yan Yan Yu; Qian Huang; Wen Long Li

doi:10.4028/www.scientific.net/AMM.513-517.1034

Paper Titles

Approximate Chinese String Matching Techniques Based on Pinyin Input Method
p.1017

Fast Matching of Astronomical Data within Data Warehouse Architecture
p.1021

Optimizing Online Assignment of Harvesting Jobs to Trans-Regional Combines
p.1026

Design and Implementation Based the SOPC of the 2D-FFT Processor
p.1030

Dual-Core FFT Processor Based on a High-Speed Real-Time Floating-Point Butterfly Processing Element
p.1034

Design and Implementation of Personnel Location System Based on Android
p.1038

Research on the Maintenance Information System Design of Typical Small Arms
p.1042

Flex: A Flexible Block-Level Distributed Storage System
p.1046

Anti-Noise Car License Plate Location Algorithm Based on Mathematical Morphology Edge Detection
p.1052

HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 513-517Dual-Core FFT Processor Based on a High-Speed...

Dual-Core FFT Processor Based on a High-Speed Real-Time Floating-Point Butterfly Processing Element

Abstract:

This paper presents a dual-core floating-point FFT processor. The internal butterfly unit of the processor based on CORDIC algorithm, and uses an iterative computation process instead of two computation process which is the complex multiplication and the evaluation of trigonometric function. The butterfly unit has nothing to do with the external memory size, so it can handle large quantities of data. Based on this unit, the processor uses two logical processing core and pipeline system to improve the throughput and instantaneity. So the design has large scope of input and high-precision operation features. Finally, we make a timing simulation for the Alteras chip of EP2C20F484C6, which can run correctly under the 100MHz system clock.

You might also be interested in these eBooks

View Preview

Info:

Periodical:

Applied Mechanics and Materials (Volumes 513-517)

Pages:

1034-1037

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.513-517.1034

Citation:

Cite this paper

Online since:

February 2014

Authors:

Jun Yang*, Yan Yan Yu, Qian Huang, Wen Long Li

Keywords:

BUF, CORDIC, FFT, FPGA

Export:

RIS, BibTeX

Price:

Permissions:

Request Permissions

* - Corresponding Author

References

[1] Tze-Yun Sung, Hsi-Chin Hsin, Yi-Peng Cheng. Low-power and high-speed CORDIC-based split-radix FFT processor for OFDM systems[J]. Digital Signal Processing, 2010 (20) 511–527.

DOI: 10.1016/j.dsp.2009.08.008

Google Scholar

[2] Yu-Wei Lin, Chen-Yi Lee. Design of an FFT/IFFT Processor for MIMO OFDM Systems[J]. Circuits and Systems, 2007 54 (4) 807–815.

DOI: 10.1109/tcsi.2006.888664

Google Scholar

[3] Chua-Chin Wang, Jian-Ming Huang, Hsian-Chang Cheng. A 2K/8K mode small-area FFT processor for OFDM demodulation of DVB-T receivers[J]. Consumer Electronics, 2005 51(1) 28-32.

DOI: 10.1109/tce.2005.1405695

Google Scholar

[4] Chung-Ping Hung, Sau-Gee Chen, Kun-Lung Chen. Design of an efficient variable-length FFT processor[J]. Circuits and Systems, 2004 2(2) 833-836.

DOI: 10.1109/iscas.2004.1329401

Google Scholar

[5] Yu-Wei Lin, Hsuan-Yu Liu, Chen-Yi Lee. A 1-GS/s FFT/IFFT processor for UWB applications[J]. Solid-State Circuits, 2005 40(8) 1726-1735.

DOI: 10.1109/jssc.2005.852007

Google Scholar

[6] Guichang Zhong, Fan Xu, Willson, A.N., Jr. A power-scalable reconfigurable FFT/IFFT IC based on a multi-processor ring[J]. Solid-State Circuits, 2006 41(2) 483-495.

DOI: 10.1109/jssc.2005.862344

Google Scholar

[7] Yuan Chen, Yu-Chi Tsao, Yu-Wei Lin, Chin-Hung Lin, Chen-Yi Lee. An Indexed-Scaling Pipelined FFT Processor for OFDM-Based WPAN Applications [J]. Circuits and Systems, 2008 55(2) 146-150.

DOI: 10.1109/tcsii.2007.910771

Google Scholar

[8] Minhyeok Shin, Hanho Lee. A high-speed four-parallel radix-24 FFT/IFFT processor for UWB applications[J]. Circuits and Systems, (2008).

DOI: 10.1109/iscas.2008.4541579

Google Scholar

[9] Guanwen Zhong, Hongbin Zheng, ZhenHua Jin, Dihu Chen, Zhiyong Pang. 1024-point pipeline FFT processor with pointer FIFOs based on FPGA[J]. VLSI and System-on-Chip, (2011).

DOI: 10.1109/vlsisoc.2011.6081654

Google Scholar