Sensitivity of Dit Extraction at the SiO2/SiC Interface Using Quasi-Static Capacitance-Voltage Measurements

Manuel Belanche; Piyush Kumar; Judith Woerle; Roger Stark; Ulrike Grossner

doi:10.4028/p-fnktjf

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HomeMaterials Science ForumMaterials Science Forum Vol. 1062Sensitivity of Dit Extraction at the SiO2/SiC...

Sensitivity of D_it Extraction at the SiO₂/SiC Interface Using Quasi-Static Capacitance-Voltage Measurements

Abstract:

In this work, we compare different quasi-static capacitance-voltage measurement systems by analyzing 4H-SiC n-type MOS capacitors and studying the influence of systematic errors when extracting the interface trap density (D_it). We show that the extracted D_it strongly depends on the calculation of the surface potential due to variations of the integration constant. In addition, the ramp-rate during the quasi-static measurement is identified as a sensitive measurement parameter whose noise level is amplified in the D_it extraction.

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Periodical:

Materials Science Forum (Volume 1062)

Pages:

346-350

DOI:

https://doi.org/10.4028/p-fnktjf

Citation:

Cite this paper

Online since:

May 2022

Authors:

Manuel Belanche*, Piyush Kumar, Judith Woerle, Roger Stark, Ulrike Grossner

Keywords:

Capacitance-Voltage Measurements, Interface Characterization, MOS Capacitor, Quasi-Static Capacitance

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Creative Commons CC BY 4.0

* - Corresponding Author

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