Modelling and Design of Pre-Equalizers for a Fully Operational Visible Light Communication System

Nowadays, Visible Light Communication (VLC) has gained much attention due to the significant advancements in Light Emitting Diode (LED) technology. However, the bandwidth of LEDs is one of the important concerns that limits the transmission rates in a VLC system. In order to eliminate this limitation, various types of equalization methods are employed. Among these, using digital pre-equalizers can be a good choice because of their simple and reusable structure. Therefore, several digital pre-equalizer methods have been proposed for VLC systems in the literature. Yet, there is no study in the literature that examines the implementation of digital pre-equalizers in a realistic VLC system based on the IEEE 802.15.13 standard. Hence, the purpose of this study is to propose digital pre-equalizers for VLC systems based on the IEEE 802.15.13 standard. For this purpose, firstly, a realistic channel model is built by collecting the signal recordings from a real 802.15.13-compliant VLC system. Then, the channel model is integrated into a VLC system modeled in MATLAB. This is followed by the design of two different digital pre-equalizers. Next, simulations are conducted to evaluate their feasibility in terms of the system’s BER performance under bandwidth-efficient modulation schemes, such as 64-QAM and 256-QAM. Results show that, although the second pre-equalizer provides lower BERs, its design and implementation might be costly. Nevertheless, the first design can be selected as a low-cost alternative to be used in the VLC system.


Preamble
Wireless communication is attracting more and more attention with the advancement of technology. With this increasing attention for wireless communication, available radio spectrum below 10 GHz has become insufficient [1]. Despite this limitation, Radio Frequency (RF)-based communication is still the most popular method used in wireless communication. However, Optical Wireless Communication (OWC) attracts increasing attention to overcome this limitation. OWC uses visible (VL), infrared (IR) and ultraviolet (UV) bands, which are in the upper parts of the electromagnetic spectrum and have features, such as being license-free and having high bandwidth [2].
Visible Light Communication (VLC) is an optical wireless communication method that uses visible light as a medium to transmit data. It should be noted that the visible light spectrum is a part of the electromagnetic spectrum, which is visible to the human eye and has a wavelength spectrum from 380 nm to 780 nm. Since the visible light source can be used for both illumination and communication, it provides extra power and cost savings compared to using two separate sources [3,4]. This feature makes the visible light spectrum

Related Work and Contributions
In the literature, several digital pre-equalizer methods have been proposed for VLC systems [13][14][15][16][17][18][19][20][21][22]. In [13], in order to improve the modulation speed of 1 MHz bandwidth white LED communication, digital FIR and matched filters were used. With the proposed approach, it was demonstrated that a data transmission rate of 20 Mbit/s can be achieved using four-level amplitude shift keying. In [14], a VLC system based on the use of digital adaptive equalizers was proposed. Experimental results demonstrated that the proposed system can offer more than 100 Mbit/s data transmission rates. In [15], to achieve higher transmission speeds, a power exponential software pre-equalization was applied to the VLC system based on a white LED. By means of experimental demonstrations, a data transmission rate of 2.08 Gbit/s over a 1 m distance was achieved with a bit error rate (BER) under 3.8 × 10 −3 . In [16], an automotive headlight VLC system with pre-equalization was proposed. Experimental results showed that a data transmission rate of 427.5 Mbit/s at a distance of 1.2 m can be achieved with BER under 3.8 × 10 −5 . In [17], a digital pre-equalization scheme that uses a luminous feedback signal at the transmitter side of a VLC system mode was proposed to mitigate the non-linearities and low-pass effect inherent to orthogonal frequency division multiplexing (OFDM)-based VLC systems. In [18], a simple approach to propose a digital pre-equalization was described. The performance of the approach was investigated by analyzing the number of time points required to represent each pre-equalized bit. In [19], a digital equalizer based on a scheme that consists of two square-root-raised-cosine filters, and a FIR filter was used to compensate the channel fading at high frequency induced by LEDs in VLC. It was shown that a transmission rate of 120 Mb/s can be realized when the 3-dB bandwidth of the LED is 13 MHz. In [20], a distributed digital pre-equalization for VLC systems based on OFDM was presented. It was demonstrated that a data transmission rate of 976.6 Mbit/s can be achieved by using distributed digital pre-equalization. In [21], a LED frequency response model was used to design a pre-equalizer. It was demonstrated that a data transmission rate of 180 Mbit/s over 1.5 m with a BER around 0.010 can be achieved using on-off keying modulation. In [22], an adaptive digital pre-equalization scheme based on a deep learning model was proposed for VLC channels. According to the experimental results, it was concluded that, with the proposed scheme, high data transmission rate can be achieved with a BER under 10 × 10 −6 .
As can be inferred from the relevant works reported in the literature, the performance of a digital pre-equalizer to be implemented in a VLC system is mostly examined in terms of BER and throughput performances in an Additive White Gaussian Noise (AWGN) channel. However, when the performance assessment of different digital pre-equalizers is concerned, it is necessary to take several factors into account. First of all, for a reliable assessment, each of the pre-equalizers needs to be tested with the same algorithm. Besides, it is necessary to use the same test environment while comparing the pre-equalizers. Furthermore, although LED is the most important component limiting the bandwidth in a VLC system, other components, such as ADC, DAC, and analogous front-ends of the VLC transmitter and VLC receiver, have significant effects on the channel. Therefore, in order to achieve more realistic results, the performance of a digital pre-equalizer implemented in a complex algorithm, that is compatible with a standard, by considering a channel containing the frequency responses of the components, can be investigated. Recently, the IEEE 802.15.13 standard has been approved for optical wireless communications applications, supporting data transmission rates of multiple Gbit/s [28]. Yet, there is no study in the literature that examines the implementation of pre-equalizers in a realistic VLC system based on the IEEE 802.15.13 standard.
In this study, it is aimed to propose digital pre-equalizers to be used in VLC systems based on the IEEE 802.15.13 standard. To this end, a fully operational VLC system was modeled in MATLAB in which the designed the pre-equalizers are utilized. That is, in order to model a realistic VLC channel for the system, a real 802.15.13-compliant VLC system was utilized in pre-equalization works. In this system, firstly, the signal recordings were collected. The recordings were then post-processed, and the channel response of the system was obtained by the channel estimation training sequence (CETS). Using the obtained channel response, a FIR filter was implemented to model the channel. Next, the channel model was added to the modelled VLC system. Furthermore, two different digital pre-equalizers were designed. In the first design, it was intended to utilize the inverse of the gain responses of the subcarriers obtained from the CETS. For this design, a post-process approach is applied in a software environment to remove CETS from the recordings. In the second design, on the other hand, a post-process is not applied, as it is based on the use of sinusoidal signals collected from a real setup. Both designs were then tested on the system. Their feasibility was comparatively assessed in terms of the BER performance under bandwidth-efficient modulation schemes, such as 64-QAM and 256-QAM. From the results, it was obtained that the system with the second pre-equalizer provides better BER performance. Yet, the first equalizer offers a low-cost option to be used in the VLC system.
The main contributions of this study can be summarized as follows: • Two different digital pre-equalizers are proposed to be used in VLC systems based on the IEEE 802.15.13 standard.

•
The effects of digital pre-equalizers on a VLC system compatible with the IEEE 802.15.13 standard are discussed for the first time in the literature.
The rest of the article is organized as follows: In Section 2, an overview of the VLC system modeled in MATLAB is presented. Here, the basic structures of the transmitter, receiver, and channel models adapted to the system are presented. Moreover, the details of the pre-equalizers designed for the system are described. In Section 3, the test results of the designed pre-equalizers implemented on the system are discussed. Finally, the article is concluded in Section 4.

VLC System Model
In order to design and implement the pre-equalizers, a VLC system was modeled in MATLAB. Figure 1 shows a block diagram of the model. As shown in the figure, the model basically consists of four main components, namely, a transmitter, a pre-equalizer, a channel, and a receiver. In the following, each of the components is described. The rest of the article is organized as follows: In Section 2, an overview of the VLC system modeled in MATLAB is presented. Here, the basic structures of the transmitter, receiver, and channel models adapted to the system are presented. Moreover, the details of the pre-equalizers designed for the system are described. In Section 3, the test results of the designed pre-equalizers implemented on the system are discussed. Finally, the article is concluded in Section 4.

VLC System Model
In order to design and implement the pre-equalizers, a VLC system was modeled in MATLAB. Figure 1 shows a block diagram of the model. As shown in the figure, the model basically consists of four main components, namely, a transmitter, a pre-equalizer, a channel, and a receiver. In the following, each of the components is described.

Transmitter and Receiver Modelling
In the system, it was aimed to achieve a data transmission rate of multiple Mbit/s. To this end, the Low Bandwidth OFDM Physical Layer (LB-PHY) algorithm defined in IEEE 802.15.13 was implemented. In the algorithm, OFDM-based modulation schemes were used. In general, since optical OFDM (O-OFDM) requires real-valued nonnegative symbols, it is not possible to use conventional OFDM directly in a VLC system [24]. Therefore, the DC-biased Optical OFDM (DCO-OFDM), which is the default modulation scheme of the IEEE 802.13.15-based LB-PHY algorithm, was used in the modelling of the transmitter and receiver.
The structure of the transmitter model is shown in Figure 2. As shown in the figure, it is composed of eight stages, namely, Convolutional Encoder, Interleaver, Modulation, Subcarrier Mapping, Inverse Fast Fourier Transform (IFFT), Channel Estimation Sequence, Pulse Shaping, and Frame Detection Sequence.

Transmitter and Receiver Modelling
In the system, it was aimed to achieve a data transmission rate of multiple Mbit/s. To this end, the Low Bandwidth OFDM Physical Layer (LB-PHY) algorithm defined in IEEE 802.15.13 was implemented. In the algorithm, OFDM-based modulation schemes were used. In general, since optical OFDM (O-OFDM) requires real-valued nonnegative symbols, it is not possible to use conventional OFDM directly in a VLC system [24]. Therefore, the DC-biased Optical OFDM (DCO-OFDM), which is the default modulation scheme of the IEEE 802.13.15-based LB-PHY algorithm, was used in the modelling of the transmitter and receiver.
The structure of the transmitter model is shown in Figure 2. As shown in the figure, it is composed of eight stages, namely, Convolutional Encoder, Interleaver, Modulation, Subcarrier Mapping, Inverse Fast Fourier Transform (IFFT), Channel Estimation Sequence, Pulse Shaping, and Frame Detection Sequence.
In Convolutional Encoder stage, the data source is encoded with convolutional coding as forward error correction. Encoded bits are sourced to the Interleaver stage to spread the errors. Then, in the Modulation stage, the data stream is modulated with QAM mapping. In the Subcarrier Mapping stage, the QAM modulation symbols are mapped into the subcarriers with respect to Hermitian symmetry, and then they are passed through the Inverse Fast Fourier Transform (IFFT). Here, Hermitian symmetry is applied to the second half of the frame in order to ensure that the output of the IFFT is real. After the IFFT, a sequence of two identical OFDM training symbols is added to estimate the channel impulse response and provide additional fine-timing synchronization. In Pulse Shaping Filter stage, the data are upsampled by a factor of 8 and filtered before the ADC process. After the In Convolutional Encoder stage, the data source is encoded with convolutional coding as forward error correction. Encoded bits are sourced to the Interleaver stage to spread the errors. Then, in the Modulation stage, the data stream is modulated with QAM mapping. In the Subcarrier Mapping stage, the QAM modulation symbols are mapped into the subcarriers with respect to Hermitian symmetry, and then they are passed through the Inverse Fast Fourier Transform (IFFT). Here, Hermitian symmetry is applied to the second half of the frame in order to ensure that the output of the IFFT is real. After the IFFT, a sequence of two identical OFDM training symbols is added to estimate the channel impulse response and provide additional fine-timing synchronization. In Pulse Shaping Filter stage, the data are upsampled by a factor of 8 and filtered before the ADC process. After the IFFT, the Frame Detection Sequence is added at the beginning of each packet to be used for packet detection and synchronization at the Receiver.
On the other hand, the structure of the receiver model is shown in Figure 3. It is composed of 10 stages, namely, Packet Detection, Match Filter, Symbol Timing, FFT, Channel Estimation, Channel Equalizer, Subcarrier Demapping, Demodulation, Deinterleaver, and Viterbi Decoder. In the receiver model, Packet Detection is responsible for finding the start point of the packet by using the original preamble sequence. Block works continuously until packet detection is succeeded. Once a packet is detected, the data are transferred to a Match Filter, which is the same filter as the Transmitter Pulse Shaping filter. The Match Filter is used to detect and correct the transmitted signal in the presence of a noisy and distorted received signal. After the incoming stream is filtered, it is sent to the Symbol Timing stage.
The Symbol Timing stage has two functions: (a) Down sampling and (b) Frame detection. Firstly, the data is down-sampled by a factor of 8 through the maximum output  In Convolutional Encoder stage, the data source is encoded with convolutional coding as forward error correction. Encoded bits are sourced to the Interleaver stage to spread the errors. Then, in the Modulation stage, the data stream is modulated with QAM mapping. In the Subcarrier Mapping stage, the QAM modulation symbols are mapped into the subcarriers with respect to Hermitian symmetry, and then they are passed through the Inverse Fast Fourier Transform (IFFT). Here, Hermitian symmetry is applied to the second half of the frame in order to ensure that the output of the IFFT is real. After the IFFT, a sequence of two identical OFDM training symbols is added to estimate the channel impulse response and provide additional fine-timing synchronization. In Pulse Shaping Filter stage, the data are upsampled by a factor of 8 and filtered before the ADC process. After the IFFT, the Frame Detection Sequence is added at the beginning of each packet to be used for packet detection and synchronization at the Receiver.
On the other hand, the structure of the receiver model is shown in Figure 3. It is composed of 10 stages, namely, Packet Detection, Match Filter, Symbol Timing, FFT, Channel Estimation, Channel Equalizer, Subcarrier Demapping, Demodulation, Deinterleaver, and Viterbi Decoder. In the receiver model, Packet Detection is responsible for finding the start point of the packet by using the original preamble sequence. Block works continuously until packet detection is succeeded. Once a packet is detected, the data are transferred to a Match Filter, which is the same filter as the Transmitter Pulse Shaping filter. The Match Filter is used to detect and correct the transmitted signal in the presence of a noisy and distorted received signal. After the incoming stream is filtered, it is sent to the Symbol Timing stage.
The Symbol Timing stage has two functions: (a) Down sampling and (b) Frame detection. Firstly, the data is down-sampled by a factor of 8 through the maximum output In the receiver model, Packet Detection is responsible for finding the start point of the packet by using the original preamble sequence. Block works continuously until packet detection is succeeded. Once a packet is detected, the data are transferred to a Match Filter, which is the same filter as the Transmitter Pulse Shaping filter. The Match Filter is used to detect and correct the transmitted signal in the presence of a noisy and distorted received signal. After the incoming stream is filtered, it is sent to the Symbol Timing stage.
The Symbol Timing stage has two functions: (a) Down sampling and (b) Frame detection. Firstly, the data is down-sampled by a factor of 8 through the maximum output energy method. With this method, the sampling points of each symbol are estimated. Frame Detection process is performed to down-sampled signals. The synchronization of OFDM symbols within a packet is also provided. The Frame Detection is performed by evaluating the cross correlation of CETS. The correlation result indicates the start and end points of an OFDM symbol. The cross-correlation operation is implemented as a FIR filter with 160 taps (coefficients), where the input of the filter is a part (400) of the detected (received) signal. Hence, after the Symbol Timing stage, synchronization within a packet is completed.
In the FFT stage, OFDM demodulation and cyclic prefix removal is applied. In order to recover the transmitted bits from the channel effects, the channel is first estimated in the Channel Estimation stage and then compensated in the Channel Equalizer. Here, the transmitted signal can be recovered by estimating the channel response at each subcarrier. Thus, the channel response of each subcarrier is estimated using the Channel Estimation Sequence, and this estimated response is then fed to the Channel Equalizer. Furthermore, a division/multiplication procedure is used to equalize the OFDM-demodulated signals. The estimated channel frequency response (inverse response of the channel) is multiplied by frequency domain OFDM symbols.
In the Subcarrier Demapping stage, the data subcarriers are demapped to data symbols, which are then sent to the Demodulation stage. In the Demodulation stage, the complex data symbols are demodulated to correct the disturbance effects of the channel. Next, the demodulated symbols are sent to the Deinterleaver stage. This is followed by a Viterbi Decoder, where the bit streams are decoded using a polynomial generator to create a Trellis Structure.

Channel Modelling
In order to model the channel, firstly, real signal recordings were collected from an IEEE 802.15.13-compliant VLC system. As shown in Figure 4, the system consists of a PHY transmitter, a Digital-to-Analog Converter (DAC), a transmitter, a LED, channel, a photodetector (PD), a receiver, an Analog-to-Digital Converter (ADC), and a PHY receiver.
OFDM symbols within a packet is also provided. The Frame Detection is performed by evaluating the cross correlation of CETS. The correlation result indicates the start and end points of an OFDM symbol. The cross-correlation operation is implemented as a FIR filter with 160 taps (coefficients), where the input of the filter is a part (400) of the detected (received) signal. Hence, after the Symbol Timing stage, synchronization within a packet is completed.
In the FFT stage, OFDM demodulation and cyclic prefix removal is applied. In order to recover the transmitted bits from the channel effects, the channel is first estimated in the Channel Estimation stage and then compensated in the Channel Equalizer. Here, the transmitted signal can be recovered by estimating the channel response at each subcarrier. Thus, the channel response of each subcarrier is estimated using the Channel Estimation Sequence, and this estimated response is then fed to the Channel Equalizer. Furthermore, a division/multiplication procedure is used to equalize the OFDM-demodulated signals. The estimated channel frequency response (inverse response of the channel) is multiplied by frequency domain OFDM symbols.
In the Subcarrier Demapping stage, the data subcarriers are demapped to data symbols, which are then sent to the Demodulation stage. In the Demodulation stage, the complex data symbols are demodulated to correct the disturbance effects of the channel. Next, the demodulated symbols are sent to the Deinterleaver stage. This is followed by a Viterbi Decoder, where the bit streams are decoded using a polynomial generator to create a Trellis Structure.

Channel Modelling
In order to model the channel, firstly, real signal recordings were collected from an IEEE 802.15.13-compliant VLC system. As shown in Figure 4, the system consists of a PHY transmitter, a Digital-to-Analog Converter (DAC), a transmitter, a LED, channel, a photodetector (PD), a receiver, an Analog-to-Digital Converter (ADC), and a PHY receiver. In the transmitting part of the system, a PHY transmitter was implemented on an FPGA device, where a bit stream was processed, which was then sourced to the DAC. The VLC transmitter (Analog Front-End: AFE) was used to drive the LED with the maximum possible amplitude in its linear region. Hence, the signal from the DAC was amplified, which was followed by the application of Bias Tee. It is important to note that the data turned out to be real due to Hermitian symmetry. However, since they are still bipolar, they are inappropriate for LED modulation. Hence, a DC bias is added to the data in order to shift the negative values to be positive and also to use the LED in its linear region before modulating the LED intensity. After the DC bias is added, the signal is transmitted by visible light with the help of the LED. Next, the signal was converted to visible light by the LED and transmitted through the LOS channel, where the LED and PD were fixed in height and distance. A reading light type LED was used in the test environment, and the bandwidth is approximately 4 MHz. Thus, it is the most bandwidth-limiting element in the channel.
In the receiving part of the system, a PD was used to capture the signal coming from the channel and convert it to the current. In order to convert the current to the voltage, a In the transmitting part of the system, a PHY transmitter was implemented on an FPGA device, where a bit stream was processed, which was then sourced to the DAC. The VLC transmitter (Analog Front-End: AFE) was used to drive the LED with the maximum possible amplitude in its linear region. Hence, the signal from the DAC was amplified, which was followed by the application of Bias Tee. It is important to note that the data turned out to be real due to Hermitian symmetry. However, since they are still bipolar, they are inappropriate for LED modulation. Hence, a DC bias is added to the data in order to shift the negative values to be positive and also to use the LED in its linear region before modulating the LED intensity. After the DC bias is added, the signal is transmitted by visible light with the help of the LED. Next, the signal was converted to visible light by the LED and transmitted through the LOS channel, where the LED and PD were fixed in height and distance. A reading light type LED was used in the test environment, and the bandwidth is approximately 4 MHz. Thus, it is the most bandwidth-limiting element in the channel.
In the receiving part of the system, a PD was used to capture the signal coming from the channel and convert it to the current. In order to convert the current to the voltage, a Transimpedance Amplifier (TIA) was used in VLC Receiver (AFE). The output of the receiver was then connected to the ADC to be processed by the PHY receiver. Similar to the PHY transmitter, the PHY receiver was also implemented on an FPGA device. It is worth noting that the sampling frequency of the ADC and DAC was set at 200 MHz. Since the up-sampling rate of the algorithm used in the transmitter model was set to 8, a 25 MHz bandwidth was chosen to be used in the system.
Channel response can be examined in three parts as Transmitter, Receiver, and Air. In this case, the Transmitter Response, H T ( f ), consists of DAC, LED, and VLC Transmitter responses: Receiver Response, H R ( f ), consists of ADC, PD, and VLC Receiver responses: The signals obtained from the ADC process were recorded in order to observe the channel response so that the effects of the components, such as the DAC, LED, VLC transmitter, channel, PD, and VLC receiver, on the transmitted signal could be taken into account.
After collecting the recordings, they were post-processed in MATLAB, and the channel response of the system was obtained with help of CETS. More specifically, CETS consisted of two OFDM symbols where the disruptive effects of the channel could be observed. It should be noted that there are 64 subcarriers in the algorithm, since the subcarriers are Hermitian Symmetric. Therefore, only the gain of the first 32 subcarriers was used to create the channel model. The gain of each subcarrier was calculated by averaging the gain of two OFDM symbols. The calculated gains were then used to model the channel response, which was modelled as a 401 tap FIR filter. Finally, the channel model was integrated into the modelled VLC system.

Pre-Equalizer Designs
Two different pre-equalizers were designed to be used in the VLC system model. In the following, the designs of the proposed pre-equalizers are briefly introduced. The general purpose in Pre-Equalizer designs, assuming a frequency response of H P ( f ), is to eliminate the disruptive effects of the channel by applying the inverse of the channel response, assuming H( f ). Once the channel response is estimated, then the frequency response of the pre-equalizer can be approximated: Then, the overall system response can be written as: where; S( f ) is the desired response, while S R ( f ) is the received response after the preequalization. Then, the design of the pre-equalizer is needed to remove channel-induced effects. A perfectly estimated channel response along with a perfectly constructed preequalizer remove all channel effects perfectly. In practice, however, it is almost impossible, especially in multi-carrier systems. Here, we implement two FIR-based pre-equalizers and demonstrate that channel effects are greatly reduced in a fully operational VLC system, a multi-carrier operated system.

Pre-Equalizer 1
For the first pre-equalizer, the main idea was to use the inverse of the gain responses of each subcarrier that could be obtained from the CETS. Therefore, the same method used to collect signal recordings for channel modelling was utilized in the first design. In this context, after the modelled channel was integrated between the transmitter and receiver in the VLC system model, the transfer was initiated by the transmitter, and CETS was recorded in the receiver. The channel response of each subcarrier was then obtained from CETS, and the inverse of these responses was used to create a 201 tap FIR filter as a pre-equalizer.
The comparison of the normalized gain responses of the first 32 subcarriers in the channel and the first pre-equalizer are shown in Figure 5. It can be clearly observed from the figure that the channel model behaves similar to a low-pass filter, whereas the pre-equalizer behaves similar to a high-pass filter. recorded in the receiver. The channel response of each subcarrier was then obtained from CETS, and the inverse of these responses was used to create a 201 tap FIR filter as a preequalizer.
The comparison of the normalized gain responses of the first 32 subcarriers in the channel and the first pre-equalizer are shown in Figure 5. It can be clearly observed from the figure that the channel model behaves similar to a low-pass filter, whereas the preequalizer behaves similar to a high-pass filter.

Pre-Equalizer 2
In the design of the second pre-equalizer, single tone sinusoidal signals were generated with a frequency range from 1 MHz to 25 MHz in 1 MHz steps. The generated signals were then transmitted to the channel in the VLC system model. A FFT process was applied to the signals received from the channel. Thus, the amplitude value corresponding to the relevant frequency was obtained. In this case, the channel response was also obtained for each frequency in the bandwidth. Hence, the 201 tap pre-equalizer filter was created by using the inverse of the calculated channel response.

Simulations and Results
The proposed pre-equalizers were tested on the VLC system designed in the previous section to evaluate their feasibility in terms of BER performance. For this purpose, simulations were conducted in MATLAB. In the simulations, a random bit stream, consisting of 1.6376 × 10 3 bits, was generated and transmitted to the designed pre-equalizer filters. Then, the subcarriers, which were equalized with respect to the frequency response, were amplified 16 times and sent to the channel. The data formed after the channel were passed through the receiver. Finally, a BER analysis was carried out. During the BER analysis, the maximum packet size defined in the IEEE 802.13.15 (2047 bytes) standard was used. The simulations were carried out 1000 times for the VLC system with and without pre-equalizer designs.
On the other hand, the LB-PHY algorithm defined in the IEEE 802.15.13 standard supports BPSK, QPSK, 16-QAM, and 64-QAM modulation schemes. Among these

Pre-Equalizer 2
In the design of the second pre-equalizer, single tone sinusoidal signals were generated with a frequency range from 1 MHz to 25 MHz in 1 MHz steps. The generated signals were then transmitted to the channel in the VLC system model. A FFT process was applied to the signals received from the channel. Thus, the amplitude value corresponding to the relevant frequency was obtained. In this case, the channel response was also obtained for each frequency in the bandwidth. Hence, the 201 tap pre-equalizer filter was created by using the inverse of the calculated channel response.

Simulations and Results
The proposed pre-equalizers were tested on the VLC system designed in the previous section to evaluate their feasibility in terms of BER performance. For this purpose, simulations were conducted in MATLAB. In the simulations, a random bit stream, consisting of 1.6376 × 10 3 bits, was generated and transmitted to the designed pre-equalizer filters. Then, the subcarriers, which were equalized with respect to the frequency response, were amplified 16 times and sent to the channel. The data formed after the channel were passed through the receiver. Finally, a BER analysis was carried out. During the BER analysis, the maximum packet size defined in the IEEE 802.13.15 (2047 bytes) standard was used. The simulations were carried out 1000 times for the VLC system with and without pre-equalizer designs.
On the other hand, the LB-PHY algorithm defined in the IEEE 802.15.13 standard supports BPSK, QPSK, 16-QAM, and 64-QAM modulation schemes. Among these schemes, due to its higher bandwidth efficiency rate compared to other lower order QAMs, 64-QAM was chosen to be used in the simulations. In addition, in order to verify the feasibility of the proposed pre-equalizers in other higher-order QAMs, 256-QAM was also used in the simulations, although it is not supported by the standard. The code rate was fixed at 3 4 before conducting the simulations.
The experimental results in terms of BER are listed in Table 1. Constellation diagrams of 64-QAM for the VLC system without pre-equalizer, with first pre-equalizer, and with second pre-equalizer are shown in Figure 6a-c, respectively. Moreover, constellation diagrams of 256-QAM for the VLC system without pre-equalizer, with first pre-equalizer, and with second pre-equalizer are shown in Figure 7a-c, respectively.
The results achieved from the simulations can be discussed in two aspects: (1) the effects of the proposed pre-equalizers on the system's BER performance, (2) the BER performance of the system with the proposed equalizers under bandwidth-efficient modulation schemes, such as 64-QAM and 256-QAM. From the results listed in Table 1, it is clear that the BER performance of the system without a pre-equalizer is poor under a higher level of QAM modulation schemes. Specifically, the BER values of the system without pre-equalizers are 19,900 × 10 −5 and 35,000 × 10 −5 for 64-QAM and 256-QAM, respectively. Yet, the BER performance of the system is considerably improved with the proposed pre-equalizers. schemes, due to its higher bandwidth efficiency rate compared to other lower order QAMs, 64-QAM was chosen to be used in the simulations. In addition, in order to verify the feasibility of the proposed pre-equalizers in other higher-order QAMs, 256-QAM was also used in the simulations, although it is not supported by the standard. The code rate was fixed at ¾ before conducting the simulations. The experimental results in terms of BER are listed in Table 1. Constellation diagrams of 64-QAM for the VLC system without pre-equalizer, with first pre-equalizer, and with second pre-equalizer are shown in Figure 6a-c, respectively. Moreover, constellation diagrams of 256-QAM for the VLC system without pre-equalizer, with first pre-equalizer, and with second pre-equalizer are shown in Figure 7a-c, respectively.  As can be seen in Table 1, when 64-QAM is used, the BER value of the system with the first equalizer is found to be 0.438 × 10 −5 . However, when 256-QAM is used, the BER value of the system with the first equalizer is reduced, which is found to be 2700 × 10 −5 . Nevertheless, the achieved BER performance is acceptable, which allows the first equalizer to be used for 256-QAM signals.
On the other hand, for the system with the second equalizer, a BER of 0 is achieved under 64-QAM, while a BER of 6.65 × 10 −5 is achieved under 256-QAM. This suggests that the system with the second equalizer still attains effective BER performance, although a higher level of QAM modulation scheme is used. Hence, it is evident that the system with the second pre-equalizer offers superior BER performance compared to the system with the first equalizer. The results achieved from the simulations can be discussed in two aspects: (1) the effects of the proposed pre-equalizers on the system's BER performance, (2) the BER performance of the system with the proposed equalizers under bandwidth-efficient modulation schemes, such as 64-QAM and 256-QAM. From the results listed in Table 1, it is clear that the BER performance of the system without a pre-equalizer is poor under a higher level of QAM modulation schemes. Specifically, the BER values of the system without preequalizers are 19,900 × 10 −5 and 35,000 × 10 −5 for 64-QAM and 256-QAM, respectively. Yet, the BER performance of the system is considerably improved with the proposed preequalizers.
As can be seen in Table 1, when 64-QAM is used, the BER value of the system with the first equalizer is found to be 0.438 × 10 −5 . However, when 256-QAM is used, the BER value of the system with the first equalizer is reduced, which is found to be 2700 × 10 −5 . Nevertheless, the achieved BER performance is acceptable, which allows the first equalizer to be used for 256-QAM signals.
On the other hand, for the system with the second equalizer, a BER of 0 is achieved under 64-QAM, while a BER of 6.65 × 10 −5 is achieved under 256-QAM. This suggests that the system with the second equalizer still attains effective BER performance, although a higher level of QAM modulation scheme is used. Hence, it is evident that the system with the second pre-equalizer offers superior BER performance compared to the system with the first equalizer. Simulation results show that both pre-equalizer designs significantly improve the BER performance of the VLC system. However, further discussions are needed to address the limitations in the design of the proposed pre-equalizers. In the next section, the proposed pre-equalizers are discussed in terms of design requirements.
On the other hand, again, note that the proposed pre-equalizers are fully based on implemented IEEE 802.15.13 standard, and, moreover, the VLC system implemented in this context is likely to be integrated within a platform. Based on our study survey, as a fully operational VLC model (using the relevant standard) employing pre-equalization is available for comparison, it is not easy to compare directly with available pre-equalizer performances. However, based on the constellation diagrams, as well as BER performance, we could conclude that the proposed pre-equalizer achieves quite satisfactory rates on a fully operational VLC system based on the standard.

Discussion
Although simulation results provide promising evidence for the designed equalizers, there might be some challenges and difficulties in their design phase. In this section, these concerns are briefly discussed to provide useful insights that may be ultimately important while making decisions in the design of the proposed pre-equalizers.
In the design phase of the first pre-equalizer, since the CETS is used to obtain the inverse of the gain responses of each subcarrier, it is necessary to apply a post-process approach. In this approach, the received signals (recordings) should be processed in a software environment, such as MATLAB, by employing packet detection and symbol Sensors 2023, 23, 5584 11 of 12 timing algorithms to remove CETS from the recordings, and then, FFT needs to be applied. As an alternative to the post-process, an extension that calculates the filter coefficients could be added to the PHY algorithm on hardware, such as a FPGA. This results in a dynamic preequalizer that enables us to calculate the filter coefficients easily, even if the transmission channel is changed. However, its implementation might be difficult in practice. Therefore, using the post-process approach is an easier way that could be preferred for the design of the first pre-equalizer.
Since the design of the second pre-equalizer is based on the use of sinusoidal signals, it is not necessary to apply a post-process. For this reason, the second pre-equalizer can be realized with the recordings collected from a real setup. Hence, a testing environment (measurement setup) is required to be built. In this case, however, it is not possible to provide a pre-equalizer in a dynamic structure. Thus, the filter coefficients need to be recalculated when the transmission channel is changed.
Overall, it can be concluded that, although the use of the second pre-equalizer in the VLC system provides lower BERs, its design and implementation might be costly. At the expense of relatively higher BERs, the first design can be selected to be used in the VLC system. It should be noted that, in its design, the post-process approach could be used for the sake of simplicity.

Conclusions
In this study, two digital pre-equalizers were proposed to be used in VLC systems based on the IEEE 802.15.13 standard. The proposed pre-equalizers were implemented on a VLC system modeled in MATLAB. Simulations were conducted to evaluate the BER performance of the system. According to the results, it has been shown that the BER performance of the system could be improved with the proposed pre-equalizers. In fact, the system with the second pre-equalizer provides better BER performance compared to the system with the first equalizer. However, the use of the first equalizer offers a low-cost alternative for the VLC system.