GaN/Si Heterojunction VDMOS with High Breakdown Voltage and Low Specific On-Resistance

A novel VDMOS with the GaN/Si heterojunction (GaN/Si VDMOS) is proposed in this letter to optimize the breakdown voltage (BV) and the specific on-resistance (Ron,sp) by Breakdown Point Transfer (BPT), which transfers the breakdown point from the high-electric-field region to the low-electric-field region and improves the BV compared with conventional Si VDMOS. The results of the TCAD simulation show that the optimized BV of the proposed GaN/Si VDMOS increases from 374 V to 2029 V compared with the conventional Si VDMOS with the same drift region length of 20 μm, and the Ron,sp of 17.2 mΩ·cm2 is lower than 36.5 mΩ·cm2 for the conventional Si VDMOS. Due to the introduction of the GaN/Si heterojunction, the breakdown point is transferred by BPT from the higher-electric-field region with the largest radius of curvature to the low-electric-field region. The interfacial state effects of the GaN/Si are analyzed to guide the fabrication of the GaN/Si heterojunction MOSFETs.


Introduction
Power semiconductor devices, also known as electronic power devices, are the main object of power electronics research. A vertical double-diffused MOS (VDMOS) was proposed by H.W. Collins in 1979 [1,2]. However, there is a contradictory relationship between the BV and R on,sp of VDMOS, and R on,sp increases sharply with the increase in BV. In order to alleviate this contradictory relationship, several new structures were proposed [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17]. With the advances in the technology, the functions of Si-based power devices are gradually approaching the limits of Si materials. In comparison to silicon, GaN, as a third-generation semiconductor material, possesses characteristics such as a wide bandgap and high critical breakdown electric field, making it the preferred material for high-frequency and high-power devices [8][9][10][11][12]. However, due to the technical immaturity of Si-based GaN devices in terms of source ohmic contacts and gate oxidation processes, their manufacturing poses significant challenges, resulting in difficulties achieving optimal electrode formation, greatly limiting the development and application of GaN devices [8,9].
However, challenges persist regarding the reliability of the gate oxide layer and the implementation of high-quality ohmic contacts in GaN devices. To address this issue, the introduction of heterogeneous junction structures has garnered significant attention [10,[18][19][20]. The proposed novel VDMOS device with GaN/Si heterogeneous junction combines the advantages of GaN material's wide bandgap and high breakdown field strength. Consequently, compared to traditional silicon-based power devices, this structure can achieve a higher breakdown voltage. Additionally, the GaN/Si VDMOS device combines mature Si process technologies to enable the formation of high-quality ohmic contacts. Therefore, in contrast to Si-based GaN devices, this structure allows for the use of mature Si process technologies in gate oxide and ohmic contact, significantly reducing the manufacturing challenges and achieving high-quality gate oxide and ohmic contact [21][22][23][24][25][26].
Si process technologies in gate oxide and ohmic contact, significantly reducing the facturing challenges and achieving high-quality gate oxide and ohmic contact [21 The GaN/Si VDMOS device optimizes the contradictory relationship between Ron,sp through a breakdown point transfer technique (BPT). In traditional Si VDMO age current accumulates in area A (as shown in Figure 1), which means that the down point of traditional Si VDMOS is located at the bottom of the P-base region w largest curvature radius and the N-drift region (area A in Figure 1). When the electric field at this point reaches the critical breakdown field strength of Si, tradit VDMOS experiences breakdown in area A. In the case of GaN/Si VDMOS, the current accumulates in area B (as shown in Figure 1). Although the highest electric formed at area A, it does not reach the critical breakdown field strength of the GaN rial in GaN/Si VDMOS. Instead, the lower electric field in area B eventually reac critical breakdown field strength of Si under a high drain voltage, causing breakd area B of GaN/Si VDMOS. This means that the breakdown in SiC/Si VDMOS dev transferred from area A with the largest curvature radius to area B through the brea point transfer technique, similar to RESUEF and REBULF technologies, by reduc highest electric field to improve BV. While breakdown still occurs in the Si mate breakdown voltage of GaN/Si VDMOS achieved a significant improvement, sur that of traditional Si VDMOS. TCAD simulation results demonstrate that the BV of VDMOS is 2029 V, and the Ron,sp is 17.2 mΩ·cm 2 , effectively breaking the constra tionship between BV and Ron,sp. Therefore, a promising avenue is opened up for th opment of vertical devices for future power applications.  Figure 1 depicts the cross-section of GaN/Si VDMOS. The preparation of G strate provides a guarantee when achieving vertical GaN power devices [8]. Firstl type GaN layer is epitaxially grown on the N + GaN substrate. Then, at room temp (25 °C), GaN-Si can be directly wafer bonded through surface-activated bonding ( method that reduces surface energy through chemical bonding and achieves stron ing at the atomic scale, thereby addressing the annealing and thermal stress issues by mismatched thermal expansion coefficients. This process facilitates the fabric GaN/Si heterogeneous junctions [27]. Subsequently, on the Si material, the P-w  Figure 1 depicts the cross-section of GaN/Si VDMOS. The preparation of GaN substrate provides a guarantee when achieving vertical GaN power devices [8]. Firstly, an Ntype GaN layer is epitaxially grown on the N + GaN substrate. Then, at room temperature (25 • C), GaN-Si can be directly wafer bonded through surface-activated bonding (SAB), a method that reduces surface energy through chemical bonding and achieves strong bonding at the atomic scale, thereby addressing the annealing and thermal stress issues caused by mismatched thermal expansion coefficients. This process facilitates the fabrication of GaN/Si heterogeneous junctions [27]. Subsequently, on the Si material, the P-well, N + source, and P + region are formed through ion implantation to enable the formation of ohmic contacts for the channel and source regions.

Materials and Methods
In this study, the two-dimensional numerical simulation of GaN/Si VDMOS was conducted using the ISE-TCAD simulation software. The main physics models include Mobility (DopingDep High Field Sat Enormal), EffectiveIntrinsic Density (OldSlotboom), Recombination (SRH (DopingDep), and Auger Avalanche (Eparal)). The criterion of breakdown is BreakCriteria {Current (Contact = "drain" Absval = 1 × 10 −7 )}. The breakdown condition was defined as the point at which the ionization integral equals unity. The parameter is Material = "GaN". The coordinates make it necessary to optimize the parameters in the numerical simulations. Some of the device parameters in the simulation are presented in Table 1. The ambient temperature is 300 K, the breakdown voltage (BV) is obtained at V GS = 0 V, and the specific on-resistance (R on,sp ) is obtained at V GS = 10 V, and the simulation results are as shown in Table 2. Table 1. Device parameters in the simulation.

Device
Si VDMOS GaN/Si VDMOS D Si is the thickness of Si for the GaN/Si VDMOS. T GaN is the depth of the GaN at the P-base region. L D is the length of Ndrift region. N D is the concentration of Ndrift region. N SUB is the concentration of P-substrate. N P is the concentration of P-base region.

Results and Discussion
The vertical electric field for GaN/Si VDMOS and conventional Si VDMOS is shown in Figure 2. In the case of Si VDMOS, when X = 2.5 µm, the maximum field strength reaches 2.55 × 10 5 V/cm (reaching the critical breakdown electric field of Si materials), resulting in a BV of 374 V for Si VDMOS [19,20]. On the other hand, in GaN/Si VDMOS, when the drain voltage reaches 374 V, the electric field at the interface between the P base and the N-type drift region does not reach the critical breakdown field strength of GaN materials; therefore, the device does not breakdown. As the drain voltage continues to increase, the electric field strength of the device rises until the electric field at the heterojunction reaches 2.85 × 10 5 V/cm (reaching the critical breakdown field of the Si materials), leading to the breakdown of GaN/Si VDMOS. Therefore, the BV of GaN/Si VDMOS increases from 374 V to 2029 V compared to the conventional Si VDMOS [21,22]. Figure 3a illustrates the blocking characteristics of GaN/Si VDMOS and Si VDMOS. Under the same bias conditions, the proposed GaN/Si VDMOS exhibits a significantly higher BV compared to conventional Si VDMOS. The results demonstrate that the BV of GaN/Si VDMOS is 2029 V, which is 443% higher than Si VDMOS. This improvement is attributed to the introduction of the GaN/Si heterojunction, which shifts the breakdown point of the new structure from a high-electric-field region (area A in Figure 1) to a lowelectric-field region (area B in Figure 1), greatly increasing the breakdown voltage of the device. Figure 3b represents the output characteristics of GaN/Si VDMOS and Si VDMOS.
When a sufficiently large positive bias voltage is applied to the gate, an n-channel inversion layer is formed in the p-well of the GaN/Si VDMOS, allowing for the current to flow from the drain to the source. In the case of GaN/Si VDMOS, the inversion channel forms between the N + source region and the Ndrift region beneath the gate oxide layer, on the Si side. The device's resistance primarily depends on the channel resistance (R ch ) and the JFET resistance (R JFET ). The introduction of a GaN/Si heterojunction effectively adjusts the value of R ch , thereby influencing the overall resistance of the device. When the gate is positively biased, the GaN/Si VDMOS is in the on-state. The built-in electric field increases the electric field in the inversion layer, increasing the number of electrons in the channel and consequently increasing the electron current, resulting in a lower specific on-resistance of the device. The R on,sp of GaN/Si VDMOS is 17.2 mΩ·cm 2 , which is 53% lower than that of conventional Si VDMOS. Figure Figure 3a illustrates the blocking characteristics of GaN/Si VDMOS an Under the same bias conditions, the proposed GaN/Si VDMOS exhibits a higher BV compared to conventional Si VDMOS. The results demonstrate GaN/Si VDMOS is 2029 V, which is 443% higher than Si VDMOS. This im attributed to the introduction of the GaN/Si heterojunction, which shifts th point of the new structure from a high-electric-field region (area A in Figu electric-field region (area B in Figure 1), greatly increasing the breakdown device. Figure 3b represents the output characteristics of GaN/Si VDMOS an When a sufficiently large positive bias voltage is applied to the gate, an n-c sion layer is formed in the p-well of the GaN/Si VDMOS, allowing for the c from the drain to the source. In the case of GaN/Si VDMOS, the inversion c between the N + source region and the Ndrift region beneath the gate oxide Si side. The device's resistance primarily depends on the channel resistance JFET resistance (RJFET). The introduction of a GaN/Si heterojunction effective   GaN/Si VDMOS       induces an internal electron barrier in the inversion layer at the GaN/Si heterojunction. This enhances the internal electric field at the GaN/Si interface and changes the distribution of the electric field, resulting in an increase in the BV and R on,sp . As the concentrations of acceptor-like interface state charges increase from 1 × 10 11 cm −2 to 5 × 10 11 cm −2 , the BV of GaN/Si VDMOS increases from 2057 V to 2308 V (shown in Figure 5a), the R on,sp increases from 17.7 mΩ·cm 2 to 118.2 mΩ·cm 2 for L D = 20 µm (shown in Figure 5b), while the V TH of GaN/Si VDMOS decreases from 4.65 V to 4.64 V (shown in Figure 5c). The increase in acceptor-like interface state charges reduces the internal electric field at the GaN/Si heterojunction. Consequently, the internal electron barrier is induced in the inversion layer at the GaN/Si interface, leading to an increase in the electron channel current. The R on,sp drops from 16.8 mΩ·cm 2 to 16.2 mΩ·cm 2 due to the concentrations of interface state charges (donor) from 1 × 10 11 cm −2 increasing to 5 × 10 11 cm −2 (shown in Figure 5b), respectively; the BV are 2000 V and 1732 V (shown in Figure 5a), and the V TH of GaN/Si VDMOS increases from 4.69 V to 4.71 V (shown in Figure 5c). paper can be either donor (electron) or acceptor (hole). Compared to the conventional Si VDMOS (BV = 374 V, Ron,sp = 36.5 mΩ·cm 2 , VTH = 5.55 V), the GaN/Si VDMOS without interface state charge exhibits an improved performance with a BV of 2029 V, Ron,sp = 17.2 mΩ·cm 2 , and VTH = 4.67 V. The introduction of a p-type trap layer by acceptor interface charge induces an internal electron barrier in the inversion layer at the GaN/Si heterojunction. This enhances the internal electric field at the GaN/Si interface and changes the distribution of the electric field, resulting in an increase in the BV and Ron,sp. As the concentrations of acceptor-like interface state charges increase from 1 × 10 11 cm −2 to 5 × 10 11 cm −2 , the BV of GaN/Si VDMOS increases from 2057 V to 2308 V (shown in Figure 5a), the Ron,sp increases from 17.7 mΩ·cm 2 to 118.2 mΩ·cm 2 for LD = 20 µm (shown in Figure 5b), while the VTH of GaN/Si VDMOS decreases from 4.65 V to 4.64 V (shown in Figure 5c). The increase in acceptor-like interface state charges reduces the internal electric field at the GaN/Si heterojunction. Consequently, the internal electron barrier is induced in the inversion layer at the GaN/Si interface, leading to an increase in the electron channel current. The Ron,sp drops from 16.8 mΩ·cm 2 to 16.2 mΩ·cm 2 due to the concentrations of interface state charges (donor) from 1 × 10 11 cm −2 increasing to 5 × 10 11 cm −2 (shown in Figure 5b  The influence of different interface state charge (donor) on the energy band diagram of GaN/Si VDMOS is shown in Figure 6a. As the interface concentration increases, more electrons are induced in the inversion layer at the GaN/Si heterojunction interface. This leads to an increase in the number of electrons in the channel, resulting in a decrease in R on,sp . Additionally, the decrease in the barrier height causes a reduction in the BV of the GaN/Si VDMOS. Figure 6b shows the influence of different interface state charges (acceptorlike) on the energy band diagram of GaN/Si VDMOS. The introduction of acceptor interface charge at the GaN/Si heterojunction interface increases the barrier height difference at the heterojunction. Consequently, the barrier height becomes higher as the interface concentration increases. Further, the BV and the R on,sp of the GaN/Si VDMOS increase (shown in Figure 3a,b).
GaN/Si VDMOS with the different concentrations of interface state charge.
The influence of different interface state charge (donor) on the energy band diagra of GaN/Si VDMOS is shown in Figure 6a. As the interface concentration increases, mo electrons are induced in the inversion layer at the GaN/Si heterojunction interface. T leads to an increase in the number of electrons in the channel, resulting in a decrease Ron,sp. Additionally, the decrease in the barrier height causes a reduction in the BV of t GaN/Si VDMOS. Figure 6b shows the influence of different interface state charges (acce torlike) on the energy band diagram of GaN/Si VDMOS. The introduction of acceptor terface charge at the GaN/Si heterojunction interface increases the barrier height diff ence at the heterojunction. Consequently, the barrier height becomes higher as the int face concentration increases. Further, the BV and the Ron,sp of the GaN/Si VDMOS increa (shown in Figure 3a The influence of different interface state charges concentrations on the characterist of the GaN/Si VDMOS is shown in Figure 7. The device is positively biased, with the g being forward-biased, causing changes in the internal electric field at the GaN/Si hete junction as the concentration and type of interface state charges vary. Compared w GaN/Si VDMOS without an interface state charge, the BV increased due to an elevation The influence of different interface state charges concentrations on the characteristics of the GaN/Si VDMOS is shown in Figure 7. The device is positively biased, with the gate being forward-biased, causing changes in the internal electric field at the GaN/Si heterojunction as the concentration and type of interface state charges vary. Compared with GaN/Si VDMOS without an interface state charge, the BV increased due to an elevation in the concentration of acceptor-like interface state charges. This is because the p-type trap layer is introduced by the interfacial charge (acceptorlike) at the GaN/Si heterojunction, resulting in the increase in the BV. When the concentrations of acceptor-like interface state charges increase from 1 × 10 11 cm −2 to 5 × 10 11 cm −2 , the BV of GaN/Si VDMOS increases from 2057 V to 2308 V, and the R on,sp increases from 17.7 mΩ·cm 2 to 118.2 mΩ·cm 2 for L D = 20 µm. On the other hand, an increase in the concentration of donor-like interface state charges results in a decrease in the internal electric field at the GaN/Si heterojunction. This induces an internal electron barrier in the inversion layer at the GaN/Si interface and increases the number of electrons in the channel, thereby augmenting the electron current. This results in a lower R on,sp when the concentrations of interface state charges are 0, 1 × 10 11 cm −2 , 3 × 10 11 cm −2 and 5 × 10 11 cm −2 , respectively; the R on,sp drops from 17.2 mΩ·cm 2 to 16. as the interface state concentration increases, the BV of GaN/Si VDMOS rises from 2057 V to 2308 V. Simultaneously, due to the presence of the p-type trap layer, the electron concentration in the inversion channel is significantly reduced, leading to an increase in the R on,sp of the device. As the interface state concentration increases, the Ron,sp of GaN/Si VDMOS increases from 17.7 mΩ·cm 2 to 118.2 mΩ·cm 2 . It can be observed that a decrease in D Si significantly improves the BV. This is because a decrease in D Si implies an increased distance between the heterojunction and area A, thereby increasing the electric field difference between area A and area B (as shown in Figure 1). Consequently, the breakdown point shifts to a lower-electric-field region, with lower electric field in area B and higher electric field in area A, resulting in a further increase in the BV of GaN/Si VDMOS. Meanwhile, as D Si increases, the influence of the built-in electric field on the electric field in the inversion layer decreases, leading to an increase in the R on,sp .  The influence of different concentrations of acceptor-like interface state charges on DSi for GaN/Si VDMOS is illustrated in Figure 8a, while the effect of different concentrations of donor-like interface state charges on DSi for GaN/Si VDMOS is shown in Figure  8b. The internal electric field at the GaN/Si heterojunction varies with the concentration and type of interface state charge. When the interface state type is acceptor-like, a p-type trap layer is introduced at the GaN/Si heterojunction, altering the built-in electric field at the heterojunction and increasing the breakdown voltage of the device. For DSi = 0.5 µm, as the interface state concentration increases, the BV of GaN/Si VDMOS rises from 2057 V to 2308 V. Simultaneously, due to the presence of the p-type trap layer, the electron concentration in the inversion channel is significantly reduced, leading to an increase in the Ron,sp of the device. As the interface state concentration increases, the Ron,sp of GaN/Si VDMOS increases from 17.7 mΩ·cm 2 to 118.2 mΩ·cm 2 . It can be observed that a decrease in DSi significantly improves the BV. This is because a decrease in DSi implies an increased distance between the heterojunction and area A, thereby increasing the electric field difference between area A and area B (as shown in Figure 1). Consequently, the breakdown point shifts to a lower-electric-field region, with lower electric field in area B and higher electric field in area A, resulting in a further increase in the BV of GaN/Si VDMOS. Meanwhile, as DSi increases, the influence of the built-in electric field on the electric field in the inversion layer decreases, leading to an increase in the Ron,sp.  Figure 9 shows the dependences of BV and Ron,sp on DSi and LD for GaN/Si VDMOS with the concentrations of interface state charge of −3 × 10 11 cm −2 and 3 × 10 11 cm −2 . The DSi includes the thickness of Si for the GaN/Si VDMOS. As the DSi decreases, the BV improves. This improvement is attributed to the increasing electric field difference between area A and area B, which is a result of the rising interface of the GaN/Si heterojunction and the  Figure 9 shows the dependences of BV and R on,sp on D Si and L D for GaN/Si VDMOS with the concentrations of interface state charge of −3 × 10 11 cm −2 and 3 × 10 11 cm −2 . The D Si includes the thickness of Si for the GaN/Si VDMOS. As the D Si decreases, the BV improves. This improvement is attributed to the increasing electric field difference between area A and area B, which is a result of the rising interface of the GaN/Si heterojunction and the continuing interface effect. A lower electric field is found at area B compared to area A, the higher the BV in the GaN/Si VDMOS is; meanwhile, the R on,sp increases slightly. This study considers interface state charges of donor (electron) or acceptor (hole) type, with concentrations ranging from 1 × 10 11 cm −2 to 5 × 10 11 cm −2 . Therefore, the concentrations of acceptor-like interface state charge of 3 × 10 11 cm −2 (shown in Figure 9a) and the concentrations of donor-like interface state charges of 3 × 10 11 cm −2 (shown in Figure 9b Figure 9 shows the dependences of BV and Ron,sp on DSi and LD for GaN/Si VD with the concentrations of interface state charge of −3 × 10 11 cm −2 and 3 × 10 11 cm −2 . Th includes the thickness of Si for the GaN/Si VDMOS. As the DSi decreases, the BV impr This improvement is attributed to the increasing electric field difference between a and area B, which is a result of the rising interface of the GaN/Si heterojunction an continuing interface effect. A lower electric field is found at area B compared to ar the higher the BV in the GaN/Si VDMOS is; meanwhile, the Ron,sp increases slightly study considers interface state charges of donor (electron) or acceptor (hole) type, concentrations ranging from 1 × 10 11 cm −2 to 5 × 10 11 cm −2 . Therefore, the concentratio acceptor-like interface state charge of 3 × 10 11 cm −2 (shown in Figure 9a) and the conce tions of donor-like interface state charges of 3 × 10 11 cm −2 (shown in Figure 9b is reduced compared with the conventional Si VDMOS (shown in Figure 10).

Conclusions
The novel GaN/Si VDMOS with the GaN/Si heterojunction is proposed in this letter, based on the advantages of GaN materials. The novel GaN/Si VDMOS can not only increase the BV (BV = 2029 V) but also reduces the Ron,sp (Ron,sp = 17.2 mΩ·cm 2 ) compared with the traditional Si VDMOS (BV = 374 V, Ron,sp = 36.48 mΩ·cm 2 ) because the breakdown point is transferred from the higher-electric-field region with the maximum curvature radius to the low-electric-field region by BPT. The interfacial effect of the GaN/Si heterojunction greatly affects the characteristics of the device due to the introduction of the GaN/Si heterojunction.

Conclusions
The novel GaN/Si VDMOS with the GaN/Si heterojunction is proposed in this letter, based on the advantages of GaN materials. The novel GaN/Si VDMOS can not only increase the BV (BV = 2029 V) but also reduces the R on,sp (R on,sp = 17.2 mΩ·cm 2 ) compared with the traditional Si VDMOS (BV = 374 V, R on,sp = 36.48 mΩ·cm 2 ) because the breakdown point is transferred from the higher-electric-field region with the maximum curvature radius to the low-electric-field region by BPT. The interfacial effect of the GaN/Si heterojunction greatly affects the characteristics of the device due to the introduction of the GaN/Si heterojunction.