A 13.56 MHz Low-Power, Single-Stage CMOS Voltage-Boosting Rectifier for Wirelessly Powered Biomedical Implants

Abstract

In this paper, a low-power, single-stage, active rectifier based on a new charge-pump circuit is presented to be used in biomedical implants. The proposed circuit not only rectifies the AC input voltage to a DC voltage but also amplifies the DC output voltage to a higher level. Low-loss MOS switches are used in the structure of the designed circuit to provide high power conversion efficiency. In addition, by using two comparators, the reverse leakage current is somehow eliminated, resulting in a higher increase in the power efficiency. By tying the source and bulk terminals of the utilized transistors, the body effect problem has been solved, and by connecting the p-substrate to the ground, which is the lowest voltage in the circuit, the latch-up phenomenon is eliminated without any extra circuit. The proposed rectifier is implemented and post-layout simulated in a 0.18 µm standard CMOS technology. According to the simulation results, 1.205 V output DC voltage is achieved from an AC input signal with the peak-to-peak amplitude of 1 V at the operating frequency of 13.56 MHz with a 3 kΩ load resistance. The total active area of the designed circuit is 0.167 ${\mathrm{m}\mathrm{m}}^2$ with a maximum power conversion efficiency of 98.2%, output power in the range of 0.5–1.5 mW, and voltage conversion ratio of 120%.

1. Introduction

Wireless power transfer (WPT) has been widely used in various applications, such as charging portable devices, electric vehicles, renewable energy resources, and implantable medical devices (IMDs), including retinal prostheses, cochlear implants, and neural recording microsystems [1,2,3,4,5,6]. The WPT system can effectively transmit power from the source to the targeted moving device by electromagnetic induction with a lack of radiation. It should be noted that paying attention to the health aspects of WPT systems are very important, especially in IMDs in which these magnetic fields can cause disease in humans [5,6]. As the IMDs need to be compact in size and consume low power, any efforts to simplify the circuitry or reduce its energy consumption are welcomed [2]. Providing a consistent power supply for the reliable operation of IMDs, which can be easily obtained by a battery, plays an essential role in the volume, size, and weight of the device. Prolonged battery life is another important feature that contributes to the efficiency of these devices. In most cases, there is not sufficient space for batteries that can last for a desirable lifetime of the IMDs. Moreover, there are some limitations in both total charge storage ability and the number of recharge cycles. As a result of size limitations in IMDs and the need to avoid wires to reduce the risk of infection, the wireless operation of these devices is necessary. Capacitive, inductive, and ultrasonic links are the common methods for wirelessly exchanging data between the external world and implantable devices, as well as providing power to them [4,5,6,7,8,9,10,11].

Traditionally, most IMDs use an inductive wireless power link (Figure 1) to transfer power and command signals to the implant via forward telemetry. In reverse telemetry, amplified neural signals and the status of the device’s different conditions are transferred outside the body [12]. In this case, the overall efficiency (η_Total) of the forward wireless power transmission chain is obtained as follows:

$${\eta }_{Total}={\eta }_{PA}\times {\eta }_{Coil}\times {\eta }_{AC-DC}\times {\eta }_{Reg.}$$

(1)

where η_PA is the efficiency of the power amplifier on the external side, η_Coil is the inductive coil link efficiency, η_AC-DC is the efficiency of the AC-DC converter, and η_Reg is the efficiency of the regulator circuit. Achieving higher power conversion efficiency (PCE) in inductive power supply applications is highly desirable as it allows implantable microelectronic devices to operate with less received power from a longer distance. This fact also reduces the risk of tissue damage due to overheating. In implantable devices, the efficiency of the link is limited due to the size limitation of the second coil. On the other hand, in most applications, the regulator circuit has high efficiency due to its low dropout topology. Thus, improving the efficiency of rectifiers is a crucial factor for the safe operation of IMDs [13].

In general, designing a high-efficient rectifier has its challenges. Schottky diodes are often utilized in these circuits to enhance conversion efficiency. However, considering additional costs and the fact that these devices are not supported in all CMOS processes, a CMOS-based implementation is a practical solution [14]. It is important to note that rectifiers should be able to process low-amplitude input signals. This capability can reduce the required induced voltage across the implant coil for proper operation, especially in applications such as cochlear implants. By reducing the required size of the implant coil, it allows for a minimally invasive implant [15]. It should be noted that rectifiers utilized in most wirelessly powered devices are highly inefficient at low-input levels [13,16,17,18,19,20,21]. This stems directly from the threshold voltage of devices utilized in the rectifiers, which happens in general standard CMOS transistors [22]. The need for a large-input signal to achieve high efficiency limits the operation distance of the rectifier. Furthermore, this can also lead to tissue damage or heating issues in implant applications [21]. Moreover, in RF energy-harvesting systems, the rectifier’s PCE at low-input power level is a dominant factor. Designing a rectifier with high PCE at very low-input power is a significant challenge in CMOS technology due to the power dissipated by the threshold voltage. This is especially relevant given that RF energy in the environment is typically very weak [23]. Another challenge is the body effect of the employed transistors. In the energy transfer system, there is no steady supply voltage to the transistors’ bulk. In the conventional self-body bias solution, the voltage of the body of PMOS devices will always be the highest voltage level, which is even higher than the input voltage. Therefore, this approach can result in decreased current and lower PCE [24].

We present in this work a low-power, single-stage, full-wave CMOS rectifier designed for wireless power transfer in biomedical implant applications for an industrial, scientific, and medical (ISM) band of 13.56 MHz. Compared to the previous circuit presented in [13], the proposed design offers several advantages, such as PCE and voltage conversion ratio (VCR) improvements as well as the ability to work at lower input voltages. The presented rectifier not only converts the received AC signal but also amplifies the DC output voltage level using a charge-pumping technique with the minimum number of transistors. As for the step-up charge pump, the highest possible input voltage is preferred; this circuit makes it possible to use the AC input signal with a low amplitude, and by amplifying the level of DC output voltage, reduces the number of serial stages of the charge-pump circuits. The presented design has solved the body effect problem by tying the body to the source terminal for all employed transistors. Moreover, by connecting the p-substrate to the ground, the lowest voltage in the circuit, the latch-up phenomenon is eliminated without the need to use the dynamic body bias technique or any extra circuit. In the presented work, by using two conventional comparators, the return currents from the load to the input are eliminated, and the power efficiency is increased. The rest of this paper is organized as follows. Section 2 describes the structures of conventional rectifiers that can be found in the literature. In Section 3, the proposed single-stage voltage-boosting rectifier is explained in detail. Post-layout simulation results are presented in Section 4, and Section 5 concludes the presented work.

2. Conventional Rectifier Structures

There exist several rectifier topologies for biomedical applications in the literature. Figure 2a shows the well-known full-wave diode bridge rectifier, where both Schottky and CMOS types can be used in this architecture [21]. This circuit works as a full-wave rectifier, with the corresponding diode pair turning on during each cycle to allow current flow to the output load. This topology has some limitations in achieving high PCE due to the two-threshold voltage (V_TH) drops [21]. Consequently, active rectifiers implemented by the active diodes are thus widely adopted in the wireless power transmission systems [25,26]. Figure 2b depicts a CMOS gate cross-coupled rectifier, which is discussed in more detail in [27]. One major benefit of this topology is its ability to allow for low on-resistance compared to the diode-bridge structure, thereby enabling moderate efficiency at low-input signals. However, this structure suffers from reverse leakage current that reduces PCE [21]. To overcome the reverse leakage current issue, two comparators shown in Figure 3, have been added to the circuit structure of Figure 2b [15,18,28]. To avoid latch-up and substrate leakage, potentials at separated N-well body terminals of PMOS devices need to be the highest potentials on-chip [28]. Thus, the self-body-bias circuit, shown in Figure 3c, needs to be employed in this topology to ensure that the bulk voltage is always the highest in this structure [24]. It should be noted that although many comparator-based rectifiers achieve a high PCE of over 80%, these circuits have a limitation of operating at very low frequencies [15] and require a large-input signal to achieve such high PCEs, which limits the allowed operation distance of the rectifier or may result in tissue damage/heating issues for implant applications. Moreover, in some cases, some calibration control is necessary to improve efficiency [28].

More advanced rectifier circuits have recently been proposed in [29,30,31]. In [29] a novel differential CMOS rectifier for radio frequency energy-harvesting applications is presented. The design rectifier involves adaptively deactivating the cross-coupled counterpart in the last stage of the rectifier via a self-biasing configuration. It effectively mitigates the reverse leakage current and enables efficient operation of the activated diode-based rectifier circuitry in the high-power region, extending the high-PCE range. In [30], researchers proposed a self-protected, high-efficient CMOS rectifier design, with a key innovation lying in a reverse DC-feeding, self-body-biasing technique. This technique enables the dynamic control of the threshold voltage of transistors in the rectifier circuit, thus enhancing the rectifier’s efficiency by optimizing the power transfer and reducing the voltage drop across the rectifying diode. The idea proposed in [31] describes a rectifier consisting of multiple NMOS transistors connected in series, forming a voltage multiplier structure. This configuration enables the rectifier to operate efficiently even at low-input voltages. Additionally, a gate voltage-boosting technique is employed to generate an additional voltage that is used to boost the gate voltage of the NMOS transistors. The NMOS transistors are produced using a deep n-well process in the proposed all-NMOS rectifier with the gate voltage-boosting technique, and each transistor inhabits in its own p-well to eliminate the body effect, which benefits the PCE and sensitivity of the rectifier.

3. The Proposed Voltage-Boosting Rectifier

Figure 4a shows the proposed single-stage active voltage boost rectifier to be used in an implantable biomedical microsystem. It consists of two gate cross-coupled NMOS devices (M_n1,2) for rectifying the negative cycle, two gate and source cross-coupled PMOS pairs (M_p1,2 and M_p3,4), and two flying capacitors (C_Fly1,2) for boosting and rectifying the positive cycle of the input signal. For a better understanding of how the proposed rectifier works, a diode illustration of the circuit is shown in Figure 4b. In this figure, the negative cycles of the input voltage are rectified through D₁ and D₂, and at the same time, C_Fly1 and C_Fly2 are charged via D₃ and D₄. In the next cycle, stored charges in C_Fly1 and C_Fly2 are pumped into the load through D₅ and D₆. To eliminate reverse currents that reduce the power efficiency of the circuit, two conventional comparators, which are previously shown in Figure 3b, have been added to the presented design. Figure 5 shows the proposed full-wave boost rectifier with the comparators. The operation of the proposed rectifier is explained in the following paragraphs.

For a better understanding of the operation of the proposed circuit, Figure 6 depicts the circuit in separate cycles in which the grey devices show the off transistors. As illustrated in Figure 6a, in the first cycle of the input signal, M_n1, M_p2, and M_p4 transistors are on, and the negative half-cycle is rectified through the M_n1 transistor. In this cycle, C_Fly1 is charged via the M_p2 transistor, and the C_Fly2 capacitor, which is charged in the previous cycle, is discharged through the M_p4 device to the load (pumping charges into the load). The positive half cycle is rectified in this way. In the next cycle, as it has been depicted in Figure 6b, the M_n2, M_p1, and M_p3 devices are on, and the negative half-cycle is rectified through the M_n2 transistor. C_Fly2 is charged via the M_p1 transistor, and the C_Fly1 capacitor, which is charged in the first cycle, is discharged through the M_p3 transistor to the load. Voltages of different parts of the proposed circuit are shown in Figure 7. As shown in this figure, when the pump capacitor voltage is higher than the rectified output voltage, the comparator output is low, and the corresponding PMOS device is on. As soon as the pump capacitor voltage drops below the rectifier output voltage, the comparator output is turned high, turning off the corresponding PMOS transistor. Therefore, the return currents from the output to the input are eliminated, and the power efficiency is increased. In overall, the advantages of the presented active rectifier over existing similar works are:

✓

working at low-amplitude input voltage with high power conversion efficiency,

✓

eliminating the body effect problem,

✓

eliminating the latch-up phenomenon without any extra dynamic body bias circuits, and

✓

amplifying the DC output voltage.

Table 1. Design Parameters and Transistor Dimensions of the Designed Circuit.

Component	Value
(W/L)Mp	25 µm/0.18 µm
(W/L)Mn	50 µm/0.18 µm
(W/L)MpComparator	1 µm/0.18 µm
(W/L)MnComparator	0.4 µm/0.18 µm
CFly1,2	57 PF
Freq.	13.56 MHz
|VIN|	1 V
RLOAD	3 kΩ
CLOAD	500 PF

reports the design parameters for the proposed circuit. Transistor dimensions (W/L) for the main PMOS and NMOS devices had been set to 25 µm/0.18 µm and 50 µm/0.18 µm, respectively. C_Fly1,2 are set to be 57 pF, and W/L for PMOS and NMOS transistors employed in the comparators are 1 µm/0.18 µm and 0.4 µm/0.18 µm, respectively. The selection of these design parameters is based on the operating frequency of the circuit as well as the input voltage range of 1 V. The values are chosen through tuning and optimization, taking into account the maximum PCE and VCR, and the minimum overall circuit size. Moreover, as discussed in the following section, C_LOAD value is set to 500 pF, considering the PCE and VCR behavior of the presented circuit. As it is shown in the simulation results section, the VCR and PCE performance can be improved by increasing the load capacitor. However, it can increase the overall chip area and also lead to slow transient response.

For better comparisons of the designed circuit with similar works, the output rectified voltage of the proposed design with and without comparators has been demonstrated in Figure 8. In this figure, all the circuit parameters are the same, and as it is obvious, the DC output voltage for the design with comparators is about 0.4 V more than the design without comparators. Moreover, to indicate the values of direct and reverse currents, load current diagram along with its values are shown in Figure 9. As it can be seen, the direct current is more than four times the reverse current. According to Figure 8, the power efficiencies are 98.9% and 53.12% for the scenarios with and without comparators, respectively. Thus, the power efficiency has been improved by almost 45%. It should be noted that for the PCE calculation, the following equation has been used:

$$PCE=\frac{P_{DC-out}}{P_{AC-in}}$$

(2)

where P_DC-out is the DC power of the output signal and is calculated by dividing the squared average of DC output voltage over the load resistor, as follows:

$$P_{DC-out}=\frac{{V^2}_{DC-out}}{R_{load}}$$

(3)

Additionally, P_AC-in is the AC power of the input signal. To determine P_AC-in, an integral must be taken by multiplying the input voltage and input current over a specific time period (typically consisting of several cycles) and then dividing the result by the specified time duration [13]. Since both input voltage and input current are subject to change over time, this process is crucial for accurately calculating P_AC-in. Consequently, P_AC-in is calculated as follows:

$$P_{AC-in}=\frac{1}{10T}{\int }_0^{10T}\left(I_{AC-in}\times V_{AC-in}\right)dt$$

(4)

However, for calculating the PCE, because the rectifier is designed based on the pumping charges and we have a settling time, it is better to calculate the integral of the output voltage multiplied by the output current instead of using Equation (3). Doing this, the power efficiency drops in the first few cycles, is also calculated, and more accurate calculations are performed.

The VCR is the ratio of output DC voltage (V_DC-out) divided by the input peak voltage amplitude (|V_AC-in|), which can be represented as:

$$VCR=\frac{V_{DC-out}}{\left|V_{AC-in}\right|}$$

(5)

4. Post-Layout Simulation Results

The proposed active rectifier has been implemented at the schematic level using the standard TSMC 0.18 μm CMOS process and then simulated with the Spectre simulator in the cadence environment. As it was previously mentioned, device dimensions are reported in Table 1, where transistor aspect ratios are set to have a low on-resistance. As depicted in Figure 10, the designed rectifier occupies a total silicon area of 366 µm × 456 µm. Important waveforms that resulted from the post-layout simulations in the typical NMOS and PMOS corner case when an RF signal with 13.56 MHz operating frequency and amplitude of 1 V was applied to the rectifier are reported in this section. Figure 11 shows the output voltage versus variation in the input frequency when R_LOAD is 3 kΩ with a 500-pF parallel load capacitor. As depicted in Figure 11, circuit simulations show that the presented rectifier has been designed to have a maximum output voltage in the frequency range of 13.56 MHz.

The post-layout simulated PCE and VCR dependence on the input frequency is reported in Figure 12, where input voltage (V_IN) is set to be 1 V and R_LOAD is 3 kΩ with a 500-pF parallel load capacitor. As it is obvious, both the PCE and VCR values are almost maximum around the operating frequency of 13.56 MHz. It should be noted that as the input frequency increases, the PCE decreases mainly due to the speed limitation of the comparators as well as not having enough time for charging and discharging the utilized capacitors.

Figure 13 shows PCE and VCR versus variations in load resistor with an input voltage amplitude of 1 V and operating frequency of 13.56 MHz. It can be interpreted from the simulation results that as the load resistance increases from 1 kΩ to 12 kΩ, the VCR increases, but the PCE shows a different behavior. According to the circuit simulations, PCE increases as the load resistor increases (its peak value is for 3 kΩ load resistor), and then, it reduces as the load increases. The PCE reaches its maximum at a specific load condition, which is primarily determined by the aspect ratio of MOS switches. While larger devices permit more current to flow, they also result in higher switching losses. When the load resistor has a lower value, the current flowing through the rectifier is quite high, leading to significant conduction losses and consequently, low PCE. On the other hand, when R_LOAD > 5 kΩ, static power losses and switching losses contribute to a decrease in PCE.

Figure 14 shows the simulated results for output power versus variation in load resistor. As it has been shown, the maximum amount of transfer power to the load occurs at a load resistance of 2 kΩ and it is almost 520 µW. According to the circuit simulations, output power starts to decrease when the load resistance is larger than 3 kΩ. Thus, the load resistance of 3 kΩ was selected in this design, which results in the PCE value of 98.2%, VCR = 120%, and transfer power to the load of 489 µW. It should be noted that it is always a challenging task for the designers to design a rectifier with maximum VCR and PCE, considering the output power and R_LOAD values [19]. It also must be added that the obtained amount of output power is enough for low-density neural recording microsystems [32,33].

To have more accurate circuit simulations, the PCE and VCR behaviors of the proposed active rectifier have been studied in Figure 15 and Figure 16 for different load resistor values and input signal amplitudes for the operating frequency of 13.56 MHz as well as considering different values for load resistor and operating frequency for the input signal of 1 V in Figure 17 and Figure 18. As it can be interpreted from these figures, the PCE value is the maximum when the operating frequency is almost 13.56 MHz, V_IN is around 1 V, and R_LOAD = 3 kΩ. The VCR value increases as the load resistor increases, while this happens when V_IN is around 1 V, and operating frequency is almost 13.56 MHz. To study the effect of input voltage amplitude on different output parameters (such as V_OUT, P_OUT, PCE, and VCR),

Table 2. Post-layout simulation results of the designed active rectifier for different input voltages, R_LOAD = 3 kΩ and Freq. = 13.56 MHz.

|VIN| (V)	VRect (V)	POUT (mW)	PCE (%)	VCR (%)
0.7	0.541	0.097	62	77.28
0.8	0.803	0.214	81.5	100.37
0.9	1.053	0.369	98.7	117
1	1.205	0.484	98.9	120.5
1.1	1.33	0.589	94.77	120.9
1.2	1.436	0.687	88.35	119.66
1.3	1.535	0.785	82.82	118.07
1.4	1.618	0.872	78.235	115.57
1.5	1.723	0.989	74.05	114.86
1.6	1.81	1.092	70.625	113.12
1.7	1.898	1.2	67.6	111.64
1.8	1.981	1.308	65.095	110.05
1.9	2.067	1.424	62.79	108.78
2	2.146	1.535	61.01	107.3

reports the post-layout simulation results of the designed active rectifier for different input voltages when R_LOAD is 3 kΩ and operating frequency of 13.56 MHz. According to Table 2, although an increment in the input signal amplitude will lead to more output voltage and power, PCE and VCR have their maximum values around V_IN = 1 V.

Figure 19 shows output voltage versus variation in the load resistor with an input voltage amplitude of 1 V. As it is clear in Figure 19, although an increment in the load resistance value (1 kΩ to 12 kΩ in this case) will result in more output voltage value, it should be noted that there are some tradeoffs between resistance value, output power, PCE, and VCR, which practically limit the load resistance value. According to the circuit simulation, the output voltage is almost 1.2 V for the load resistance of 3 kΩ, which is the chosen value for the load in this work.

To accurately simulate the circuit with fabrication process variations, a Monte Carlo analysis is performed on the designed active rectifier circuit in which the changes in the transistor channel length and width, channel-doping concentration, mobility, oxide thickness, and threshold voltage have been assumed to have an independent normal Gaussian distribution with the default standard deviation of 1/1. Figure 20 shows the post-layout simulated transient response of the output voltage of the proposed active rectifier for 40 iterations. As it can be seen, the effect of non-idealities on the performance of the proposed active rectifier is negligible. The Monte Carlo analysis is also performed using device models with realistic statistical distributions for PCE and VCR values. For the performed analysis, the circuit is simulated with 100 iterations, the results of which are shown in Figure 21. According to the achieved results, PCE of the designed circuit exhibits a mean value of 93.18% with the standard deviation of ~2.7 when R_LOAD is 3 kΩ and an RF signal with 13.56 MHz operating frequency and amplitude of 1 V is applied to the rectifier. Moreover, the VCR value has the mean value of 118.36% with the standard deviation of ~1.4.

Table 3. Post-layout simulated performance of the designed circuit in different process corners.

	Corner	Temperature (°C)
		−20	0	27	85
VRect (V)	SS	1.06	1.095	1.114	1.12
	SF	1.2	1.19	1.18	1.154
	FS	1.224	1.216	1.2	1.18
	FF	1.225	1.213	1.198	1.169
PCE (%)	SS	70.46	88.4	82.48	96.87
	SF	82.72	91.32	80.29	76.73
	FS	99.85	99.82	98	94.38
	FF	84.74	92.17	80.93	76.53
VCR (%)	SS	106	109.5	111.4	112
	SF	120	119	118	115.4
	FS	122.4	121.6	120	118
	FF	122.5	121.3	119.8	116.9

shows the process corner analysis results for the proposed rectifier for V_RECT, PCE, and VCR in different corners and temperatures. In the performed simulation, the same conditions for R_LOAD, RF signal-operating frequency and amplitude are applied to the rectifier.

To verify the functionality of the presented idea at the circuit level, a proof-of-concept prototype was developed using off-the-shelf components. In bench tests, a 1 kHz input signal with an amplitude of 2.5 V was applied to the circuit. Figure 22 shows an oscilloscope screen image, displaying the DC output voltage (V_Rect), which is 5.2 V, and the input signal, which supports the proposed idea.

To evaluate the overall performance of the designed active rectifier with some state-of-the-art similar designs working at a frequency of 13.56 MHz or below, the following figure of merit (FoM) is defined by the authors:

$$FOM=\frac{PCE\times VCR}{Size\times SLF}$$

(6)

where SLF is the shunt load factor and is used to address the effect of shunt load. SLF is defined as the multiplication of R_LOAD (kΩ) and C_LOAD (pF). It should be noted that although the VCR and PCE can be improved by increasing R_LOAD and C_LOAD, this can increase the overall chip area. Consequently, it is a challenging task for the designers to design a rectifier with maximum VCR and PCE by utilizing lower R_LOAD and C_LOAD values [19]. Another FoM, which calculates the VCR performance in terms of minimum |V_AC-in| and SLF effect, is defined in [19], as follow:

$${FOM}_{VCR}=\frac{VCR}{V_{AC-in}\times \sqrt[3]{SLF}}$$

(7)

According to Equation (7), higher FoM_VCR implies better VCR performance at lower R_LOAD and C_LOAD values. This FoM also presents the rectifier’s ability to operate at lower input voltages [19], which can be more appropriate for the biomedical circuits.

Table 4. Performance comparison with other similar designs.

Ref.	This Work	[13] 2018	[16] 2020	[20] 2012	[34] 2021	[35] 2022	[36] 2022
Input Amplitude (V)	1~2	1.36	1.5~5	0.8~2.7	1.8~3.3	2.5~3.3	1.6~3
Output DC (V)	1.205~2.15	1.195	1.4~4.95	0.3~2	1.63~3.06	2.27~3.08	1.48~2.92
Frequency (MHz)	13.56	13.56	3	10	13.56	13.56	6.78
RLOAD (kΩ)	3	0.19	5	2	0.5	0.5	0.5
CLOAD (F)	500 p	20 n	100 p	200 p	1 µ	2 n	100 n
Max. Output Power (mW)	0.48–1.53	7.52	0.55–3.54	2	69.8	54.5	45
Max. PCE (%)	98.9	85.5	73–86	37–80	93.2	93.1	91.2~92.8
Max. VCR (%)	120.5	88	70–78	60–89	92.6	93.4	92.7~97.5
$\mathbf{Area}\mathbf{\left(}{\mathbf{m}\mathbf{m}}^{\mathbf{2}}\mathbf{\right)}$	0.167	0.0141	N/A	0.6084	0.36	0.446	0.5194
FoM	47.57	140	N/A	29.25	0.048	19.49	0.348
FoMVCR	10.48	4.15	5.88	10.17	0.65	3.75	1.58
Sim./Meas.	PLSim. *	PLSim.	Sim.	Meas.	PLSim.	Meas.	PLSim.

* Post-Layout Simulation.

shows the comparison with prior similar designs, where the last row of Table 4 indicates whether the discussed design is verified by simulation or measurement. It is admitted that some percent of deviation is expected between simulation and experimental tests. According to the comparison done in Table 4, the designed work is among the best circuits that can be found in the literature. It should be noted that in most of the rectifier circuits, the output DC voltage level is lower than the input AC voltage level. This is normal because in the ideal case, a certain amount of voltage drops on the drain-source terminal of the employed transistors. In the presented work, the output voltage level is higher than the input voltage level because the designed rectifier is based on the charge-pump circuit. In fact, with the proper combination of the rectifier and charge-pump structures and with a fewer number of employed transistors, high power efficiency is achieved in the presented work.

5. Conclusions

This work presents a low-power, single-stage CMOS voltage-boosting rectifier, running at 13.56 MHz. The measurement results verified the effectiveness of the designed circuit. The body-effect problem and latch-up phenomenon have been solved without any extra circuit. The designed circuit is very efficient in the low-input voltage range, which is a significant problem with most previous rectifiers. According to the post-layout simulation, the PCE and VCR values are equal to 98.2% and 120%, respectively. These values are obtained as a result of an input RF signal with a peak-to-peak amplitude of 1 V, and a 3 kΩ load resistance, which will result in 1.205 V of DC output voltage. The total active silicon area is 0.167 ${\mathrm{m}\mathrm{m}}^2$.