Deep Neural Networks-Based Direct-Current Operation Prediction and Circuit Migration Design

Abstract

Recently, design methods based on $g_m/I_d$ parameters have attracted attention in analog integrated circuit design and have been automated with computer assistance. However, the look-up tables (LUTs) in the $g_m/I_d$ method have the problem of high hardware resource overhead. To address this issue, this paper proposes a multi-output deep neural network (DNN) structure for modeling the direct-current parameters of transistors and replacing LUTs for circuit design. The proposed DNN models’ performance is verified using mainstream design technologies such as TSMC 40 nm (T40), TSMC 65 nm (T65), TSMC 180 nm (T180), and SMIC 180 nm (S180). Compared with LUTs, the proposed DNN models are able to reduce at least 99.9% storage space occupation and 95.62% prediction time overhead with a mean absolute percentage error of less than 0.2%. In addition, we propose an automated circuit migration design method using DNN models in different technologies, combined with $g_m/I_d$ parameters. The method generates circuit design databases in different technologies and obtains device design results according to performance requirements. The experimental results show that using DNN models can reduce the time overhead by more than 40% compared to using LUTs. The simulation results of circuit transplantation design show that the circuit performance of T40, T65, S180, and T180 meets the requirements, which verifies the proposed DNN-based automated circuit design method.

1. Introduction

In the current era of mixed-signal system-on-chips, digital integrated circuit (IC) design has the benefit of relying on mature automated synthesis tools for automated design. In contrast, analog IC design is a time-consuming task that heavily relies on manual analysis by expert designers due to the lack of mature automated synthesis tools [1]. This manual design process is a bottleneck in IC design, prompting the need for automated analog IC design technologies, which have garnered widespread attention.

The mainstream approaches to automation can be broadly categorized into two types: optimization-based and knowledge-based methods [2]. The optimization-based approach utilizes optimization algorithms such as evolutionary algorithms [3] to generate new device size results. However, due to the inherent complexity of both algorithms and circuits, this approach may result in significant time consumption or even physically infeasible solutions [4].

The knowledge-based approach, on the other hand, relies on expert knowledge to develop automated design programs capable of generating valuable solutions. Currently, the mature approach is based on the $g_m/I_d$ method [5] with pre-computed lookup tables (LUTs) [6], which achieves high design accuracy and has been successfully applied in the design of various circuits such as operational amplifiers, bandgap reference circuits, low-noise amplifiers, and others [7,8,9,10,11].

The LUTs used in the $g_m/I_d$ method are generated by simulating the device parameters using a simulation program with integrated circuit emphasis (SPICE) models with fixed step sizes in channel length (L), $V_{ds}$, $V_{bs}$, and $V_{gs}$. For parameter values that are not present in the LUTs, interpolation can be utilized to predict the values. However, high-precision LUTs require more finely scanned parameter step sizes, leading to increased storage space usage [12]. Taking into account the number of model parameters and device types, the large storage space requirements and the need to load them into memory for access entail significant hardware resource costs, rendering this design method impractical.

With the continuous advancements in machine learning (ML), researchers have started exploring the possibility of constructing device parameter models using ML models. Habal et al. [13] developed a simple quadratic polynomial as a feature engineering input and proposed a neural network with a single hidden layer for predicting $g_m/I_d$. In the work of Habal et al., the prediction errors of the ML model were approximately controlled within 3%. However, predicting a single parameter of a transistor in a specific technology appears to be insufficient.

Yang et al. [14] conducted a thorough analysis of the impact of different activation functions in a multi-layer perceptron model for predicting the parameters of various transistors. They proposed a neural network architecture with three hidden layers and found that the inverse square root unit (ISRU) activation function provided the best training results. The mean absolute percentage error (MAPE) for the negative channel-metal-oxide-semiconductor (NMOS) was reduced to 1.38%, but the errors for the positive channel metal-oxide-semiconductor (PMOS) ranged between 6.47% and 10.69%. Although these studies demonstrate the potential of multi-layer perceptron models instead of LUTs, the challenge lies in determining the optimal hyperparameters of the neural network.

Ho et al. [15] proposed an algorithm that utilizes genetic algorithms and multi-layer perceptrons to predict current ($I_d$) using an evolved neural network. Their work demonstrated that the prediction accuracy of the evolved neural network was superior to that of a conventional multi-layer perceptron. This research provides some inspiration for our current work as it highlights the potential of using genetic algorithms to optimize neural networks and improve prediction accuracy.

Wang et al. [16] introduced a direct-current (DC) simulation-based neural network model called the DC model. This model utilizes graphics card-accelerated neural networks to capture the non-linear relationship between specific DC parameters and performance metrics. By substituting certain simulation tasks, it significantly reduces time consumption while maintaining a high level of accuracy. Qi et al. [17] proposed a knowledge-based neural network approach that segregates geometric variables from other input variables. The geometric variables are modeled using physics-based analytical equations, while the remaining variables are represented by an artificial neural network. This methodology was verified using the BSIM6 (BSIM, a simulation model developed by the UC Berkeley) model and demonstrated good agreement between the model predictions and experimental results. Similarly, Wang et al. [18] conducted similar work by modifying the BSIM model for low-temperature conditions in a 180 nm technology. They introduced an optimization model based on the backpropagation neural network prediction to compensate for the low-temperature effect. A common characteristic of the aforementioned approaches is the utilization of neural networks to substitute certain aspects of physical modeling, thereby accelerating scientific computations.

Fu et al. [19] presented a model based on the backpropagation neural network for the prediction of NMOS performance parameters. The modeling process involved employing substrate bias, substrate impurity concentration, oxide thickness, and adjusted implant doping concentration for threshold voltage as independent variables while considering threshold voltage and others as dependent variables. Following the training of the model, none of the final prediction variables exhibited an average percentage error exceeding 1.5%.

Wei et al. [20] developed a precise artificial neural network model that encompasses the complete range of drain currents. By employing the Latin hypercube sampling algorithm, they achieved a substantial reduction in the training data requirement without significantly compromising the quality of the fitting outcomes. This approach effectively mitigated training overhead. The experimental findings demonstrate that the proposed artificial neural network model exhibits excellent fitting capabilities in the 180 nm technology.

Most of the above works focus on the parametric modeling of devices, but less work applies the proposed models to actual circuit design. In addition, the technology nodes involved in device parameter modeling focus on one or two technologies, and the effectiveness of the model on more technology is unknown.

This paper introduces a new deep neural network (DNN) architecture that has multiple DC outputs for modeling complementary metal-oxide-semiconductor (CMOS) device parameters. This DNN model requires only four inputs ($V_{gs}$, $V_{ds}$, $V_{bs}$, and L) and can produce 14 outputs simultaneously, including $I_d$, $V_{th}$, $V_{dsat}$, $g_m$, $f_{ug}$, $g_{ds}$, $C_{gg}$, $C_{gs}$, $g_m/I_d$, $g_m{r}_o$, $C_{gd}$, $C_{dg}$, $r_{on}$, and $C_{dd}$. The suggested DNN architecture comprehensively models the device parameters to prevalent process design kits (PDKs) TSMC 40 nm (T40), TSMC 65 nm (T65), TSMC 180 nm (T180), and SMIC 180 nm (S180), respectively. Compared with the traditional LUTs, the proposed DNN models for each PDK occupy less storage space and have high-accuracy prediction performance. Moreover, this paper leverages the DNN models within each PDK, in conjunction with $g_m/I_d$ parameters, to achieve circuit migration design. By employing circuit multiplexing, the efficiency of analog integrated circuit design is enhanced.

The structure of the paper is organized as follows: Section 2 introduces the DNN architecture and outlines the necessary metrics requirements. In Section 3, the dataset acquisition process is described. Section 4 discusses the automated design method based on the $g_m/I_d$ parameter and DNN models. Section 5 presents the experimental results. Finally, Section 6 is the conclusions.

2. DNN Model and Performance Requirements

2.1. DNN Model Architecture

The mapping of the LUTs used in the $g_m/I_d$ method can be described in (1).

$$LU{T}_{tech,type,W}[V_{gs},V_{ds},V_{bs},L]\to [g_m,g_m/I_d,...,g_m{r}_o]$$

(1)

For a given PDK ($tech$), device type ($type$), and channel width (W), the desired device parameter results such as $g_m$ and $g_m/I_d$ can be obtained by the values of $V_{gs}$, $V_{ds}$, $V_{bs}$, and L of the transistor. Typically, LUTs are only capable of providing a single parameter value at a time, and interpolation techniques are employed to obtain parameter data that lie outside the LUTs but fall within the input range.

The non-linear relationship between the input and output of the LUTs mentioned above can be modeled using ML approaches. In this paper, a DNN model, as depicted in Figure 1, for training the aforementioned input–output relationship was proposed. The DNN model begins with four input parameters, namely $V_{gs}$, $V_{ds}$, $V_{bs}$, and L. To enhance the representation capability, a feature generation layer is incorporated to generate 74 high-order feature items, which are subsequently utilized as inputs for the DNN. The DNN architecture comprises one input layer, six hidden layers, and one output layer, employing rectified linear unit (ReLU) [21] activation for all hidden layers. The hidden layers consist of 150, 120, 120, 120, 120, and 150 neurons, respectively, and are fully connected. The output layer provides predictions for 14 parameters, encompassing $I_d$, $V_{th}$, $V_{dsat}$, $g_m$, $f_{ug}$, $g_{ds}$, $C_{gg}$, $C_{gs}$, $g_m/I_d$, $g_m{r}_o$, $C_{gd}$, $C_{dg}$, $r_{on}$, and $C_{dd}$. The feature generation algorithm is presented in Algorithm A1, and the training and prediction algorithms of DNN are shown in Algorithm A2 and Algorithm A3, respectively (Appendix A). While the hyperparameter settings for the DNN model are outlined in

Table 1. The hyperparameter settings of DNN.

Name	Value
Input layer dimensions	74
Number of hidden layers	6
Hidden layer dimension	(150,120,120,120,120,150)
Output layer dimensions	14
Activation function	ReLU
Learning rate	${10}^{-5}$
Loss function	MSE
Training epochs	1000
Optimizer	Adam
Tolerance	${10}^{-5}$
Batch size	256

.

2.2. Performance Metrics of DNN Model

While the primary motivation behind proposing the DNN model is to address the issue of extensive storage requirements associated with LUTs, it is imperative to consider its capacity to replace LUTs in circuit design while maintaining superior prediction accuracy. Furthermore, the effectiveness of model-based circuit design automation is partially contingent upon the computational speed of the model, as employing a faster prediction model within the same design framework can lead to enhanced design efficiency. In light of the aforementioned analysis, this paper introduces four evaluation metrics, including time, model size, MAPE, and maximum relative error (MRE), to evaluate the performance of the proposed model.

Table 2. The metrics and statements of the DNN models.

No.	Metric	Satement
1	Size	The storage capacity utilized by the model
2	Time	The average inference time consumed by the model for one prediction
3	MAPE	The mean absolute percentage error between the predicted value and the true value
4	MRE	The maximum relative error between the predicted value and the true value

shows the statement of each metric.

3. Data Sampling

The DNN models are trained using four PDKs: T40, T65, T180, and S180, respectively. The respective ranges and step sizes of the variables used to generate each PDK dataset are presented in

Table 3. The $V_{gs}$, $V_{ds}$, $V_{bs}$, L range and step size of transistors each PDK on the dataset.

Name	T40	T65	T180	S180	Unit
W	5	5	5	5	µm
$V_{gs}$	0.1–1.2	0.1–1.2	0.1–1.8	0.1–1.8	V
$V_{ds}$	0.1–1.2	0.1–1.2	0.1–1.8	0.1–1.8	V
$V_{bs}$	0–1.2	0–1.2	0–1.8	0–1.8	V
L	0.5–6	0.5–6	0.5–6	0.5–6	µm

The values in this table are absolute values.

. For T40 and T65, the range of $V_{gs}$ and $V_{ds}$ is set from 0.1 V to 1.2 V, with a step size of 0.02 V for both variables. Similarly, the range of $V_{bs}$ is from 0 V to 1.2 V, with a step size of 0.02 V. On the other hand, for T180 and S180, the range of $V_{gs}$ and $V_{ds}$ is extended from 0.1 V to 1.8 V, and the range of $V_{bs}$ spans from 0 V to 1.8 V, with a consistent step size of 0.02 V for both variables. The channel length (L) values vary from 0.5 µm to 6 µm, with a step size of 0.2 µm, while the channel width (W) remains fixed at 5 µm across all PDKs.

Table 4. The size and the including parameters of the dataset according to Table 3.

PDK	Size	Parameter
T40	1.4 GB	$I_d$, $V_{th}$, $V_{dsat}$, $g_m$, $f_{ug}$, $g_{ds}$, $C_{gg}$, $C_{gs}$, $g_m/I_d$, $g_m{r}_o$, $C_{gd}$, $C_{dg}$, $r_{on}$, and $C_{dd}$
T65
T180	4.4 GB
S180

Size: including PMOS and NMOS.

provides detailed information regarding the generated datasets, including their sizes and the parameters they encompass. Each dataset comprises 14 device parameters, namely $I_d$, $V_{th}$, $V_{dsat}$, $g_m$, $f_{ug}$, $g_{ds}$, $C_{gg}$ $C_{gs}$, $g_m/I_d$, $g_m{r}_o$, $C_{gd}$, $C_{dg}$, $r_{on}$, and $C_{dd}$. The dataset sizes for T40 and T65, which were saved in pickle format, were 1.4 GB space each (including both PMOS and NMOS devices). Similarly, the dataset sizes for T180 and S180 were 4.4 GB space each (including both PMOS and NMOS devices).

Prior to training, the logarithm of the 14 target parameters to be predicted was taken, and the dataset was normalized to eliminate any significant variations among the target parameter data. Subsequently, the dataset was divided into a training set, a validation set, and a test set, following a ratio of 0.81:0.14:0.05, respectively.

4. Sizing Method

Figure 2 illustrates the design flow used in this work. Specifically, the flow begins by specifying the design variables for the circuit, which include the $g_m/I_d$ and L for each transistor, as well as the passive device resistor-capacitor ($RC$) values. Subsequently, the design points for $V_{gs}$, $V_{ds}$, $V_{bs}$ for each transistor are determined using the mapping of $g_m/I_d$ and $V_{gs}$, along with the application of Kirchhoff’s voltage law (KVL) to the circuit. These design points ($V_{gs}$, $V_{ds}$, $V_{bs}$ and L) are then input into $DNN$$Models$ to obtain 14 DC parameters.

The obtained 14 DC parameters serve two purposes: firstly, they are combined with the circuit performance equations to predict the performance of the circuit. Secondly, they are utilized to solve for the channel width (W) of each transistor based on the $g_m/I_d$ method. To expedite this process, parallel computing techniques are employed. Upon traversing all the design points, the values of L, W, R, and C alongside the corresponding circuit performance are stored in the $Design$$Database$. Finally, the sizing results are outputted according to the performance specifications requirements.

To ensure the efficacy of the design, this study incorporates a parameter known as voltage saturation margin ($V_{dsmarg}$). This parameter determines whether a transistor operates in the saturation region by evaluating the condition $V_{ds}-V_{dsat}\ge V_{dsmarg}$. Any design point that includes transistors failing to satisfy the aforementioned condition is discarded. The working details of the $V_{dsmarg}$ parameter are shown in Figure 3.

The reuse of analog circuit designs represents a pivotal strategy for enhancing the efficiency of IC design. The approach employed in this paper for implementing circuit migration design is founded upon the design process outlined in Figure 2. Specifically, it entails leveraging distinct DNN models associated with different PDKs to generate the circuit design database corresponding to each respective PDK. Subsequently, the final device sizes are determined based on the performance requirements.

It is noteworthy that the methodology proposed in this paper involves traversing the design space and recurrent utilization of the DNN models for parameter prediction, which constitutes a significant portion of the overall process time. Consequently, the time-consuming nature of the model prediction phase holds great importance as it directly impacts the efficiency of circuit design database generation.

5. Results and Discussion

This section presents the performance of the proposed DNN models as well as experiments on circuit migration design. All experiments were performed on a Linux workstation with Intel(R) Xeon(R) Bronze 3204 CPU @ 1.90 GHz and 512 GB memory.

5.1. DNN Model Performance

5.1.1. The Comparison to Other ML Models

In order to demonstrate the superior performance of the proposed DNN models, a comparison is made with other ML models. The comparison encompasses traditional models such as Support Vector Regression, Ridge Regression, Bayesian Ridge, Decision Tree, Random Forest, and others [22,23,24,25,26], as well as more recent models such as TabNet, XGBoost, LightGBM, and Denominator Numerator Fit [27,28,29,30]. The evaluation metrics employed to assess the performance of these models are presented in Table 2.

Table 5. The ML models for comparison.

No.	Acronym	Full Name
1	ABR	AdaBoost Regressor
2	BGR	Bagging Regressor
3	BRR	Bayesian Ridge Regression
4	DNFit	Denominator Numerator Fit
5	DNN	Deep Neural Networks
6	DT	Decision Tree
7	EN	ElasticNet
8	GBR	Gradient Boosting Regressor
9	KNN	K-Nearest Neighbors
10	LASSO	Least Absolute Shrinkage and Selection Operator
11	LARS	Least Angle Regression
12	LL	LassoLars
13	LGBM	Light Gradient Boosting Machine
14	PAR	Passive Aggressive Regressor
15	PLSR	Partial Least Squares Regression
16	RF	Random Forest
17	RR	Ridge Regression
18	SVR	Support Vector Regression
19	TN	TabNet
20	XGBoost	Extreme Gradient Boosting

presents a comprehensive overview of the ML models employed for comparison. Notably, with the exception of the DNN models, which are multi-output, the remaining models are single-output models. Moreover, these single-output models utilize high-order features derived from feature generation as their input. In contrast to the DNN mode, these single-output models employ 116-dimensional high-order features to ensure optimal training. The feature generation process adheres to Algorithm A1, wherein the parameter settings are specified as order = 5 and overlap_order = 4.

In order to ensure a fair comparison of model performance, the training and inference processes were conducted using the Sklearn framework, with comprehensive evaluation performed across all models.

Table 6. The performance of different ML models for $I_d$ parameter on the test set.

No.	Model Name	Total Time(s)	Size(KB)	MRE	MAPE
1	DNN	0.668	2160	0.0228	0.00191
2	DNFit	0.0176	76,421	0.09	0.007
3	BGR	2.54	4,059,874	0.09	0.009
4	DT	0.00295	10158	0.16	0.009
5	RF	0.202	642,238	0.10	0.006
6	XGBoost	0.0105	730	0.12	0.019
7	BRR	0.00661	110	0.16	0.026
8	RR	0.00288	1.48	0.18	0.026
9	TN	0.101	495	0.45	0.061
10	GBR	0.0130	175.1	0.44	0.067
11	PAR	0.00148	1.73	0.42	0.108
12	ABR	0.0544	61	2.78	0.411
13	KNN	11.7	7491.1	14.59	0.145
14	LL	0.00123	2.56	23,963.87	259.37
15	LASSO	0.00178	1.56	223.35	8.28
16	LARS	0.000850	127.31	352,261.34	230.09
17	EN	0.00474	1.57	104.86	4.910
18	SVR	1.06	2079.36	32.77	0.17
19	LGBM	0.0102	69.05	54.99	2.03
20	PLSR	0.00486	2548.77	199.57	1.49

presents the performance results of these models on the test set, which comprised approximately 10,000 data points, specifically focusing on the prediction of the T65 NMOS transistor device parameter $I_d$. Based on the evaluation metrics MAPE and MRE, the proposed DNN model outperforms all other models, with DNFit, BGR, DT, RF, XGBoost, BRR, RR, and TN models following in descending order. However, when considering the aspect of model size, the DNFit, BGR, DT, and RF models, despite exhibiting high accuracy, are notably larger compared to the proposed DNN model. In cases where all 14 parameters are taken into account, these models approach or surpass the size of LUTs. Nevertheless, after XGBoost, BRR, and TN models achieve all 14 parameter models, their total sizes either become comparable to that of the DNN model or their accuracy becomes less dominant. Regarding prediction time, when making approximately 10,000 predictions, the DNN model requires a total of 0.688 s. It is important to note that the DNN model outputs 14 parameters per prediction. From this perspective, considering an equivalent number of parameter predictions, the prediction time of the DNN model still exhibits commendable performance in both high-precision and low-storage occupation models.

To further demonstrate the superiority of the proposed multi-output DNN models, a performance comparison is conducted with single-output DNN models.

Table 7. The hyperparameters settings of single-output DNN.

Name	Value
Input layer dimensions	116
Number of hidden layers	5
Hidden layer dimension	(110,100,100,100,110)
Output layer dimensions	1
Activation function	ReLU
Learning rate	${10}^{-5}$
Loss function	MSE
Training epochs	1000
Optimizer	Adam
Tolerance	${10}^{-5}$
Batch size	256

provides the hyperparameter settings for the single-output DNN models, while

Table 8. The performance comparison between multi-output and single-output DNN models on T65 NMOS $I_d$ parameter on the test set.

Name	Total Time (s)	Size (KB)	MRE	MAPE
Multi-output DNN	0.6680	2160	0.0228	0.00191
Single-output DNN	0.0353	2302	0.0332	0.00297

presents the performance comparison between the single-output and multi-output DNN models in predicting the T65 NMOS $I_d$ parameter. In evaluating the results, it can be observed that the model size of the single-output DNN models and the multi-output DNN models are comparable, indicating that the multi-output model possesses an advantage in terms of model size. When considering all 14 parameters, the total size of the single-output model is 14 times that of a single model. Regarding prediction time, the time cost for predictions of the single-output model becomes similar to that of the multi-output model once the number of predicted parameters becomes equivalent. In terms of prediction results for the $I_d$ parameter, both the MRE and MAPE of the multi-output DNN models are smaller compared to the single-output DNN models. This indicates that the multi-output DNN models achieve higher accuracy in predicting the $I_d$ parameter.

Table 9. The MRE and MAPE results of DNN models between multi-output and single-output on the test set.

PDK	Device	Parameters	Multi-Output		Single-Output
			MAPE	MRE	MAPE	MRE
T65	NMOS	$I_d$	$1.91\times {10}^{-3}$	$2.28\times {10}^{-2}$	$2.97\times {10}^{-3}$	$3.32\times {10}^{-2}$
		$V_{th}$	$9.40\times {10}^{-5}$	$1.18\times {10}^{-3}$	$6.74\times {10}^{-5}$	$8.78\times {10}^{-4}$
		$V_{dsat}$	$6.80\times {10}^{-4}$	$8.24\times {10}^{-3}$	$5.25\times {10}^{-4}$	$7.98\times {10}^{-4}$
		$g_m$	$1.75\times {10}^{-3}$	$2.88\times {10}^{-2}$	$2.88\times {10}^{-4}$	$6.19\times {10}^{-2}$
		$f_{ug}$	$1.85\times {10}^{-3}$	$2.01\times {10}^{-2}$	$2.26\times {10}^{-4}$	$3.29\times {10}^{-2}$
		$g_{ds}$	$2.19\times {10}^{-3}$	$2.08\times {10}^{-3}$	$3.53\times {10}^{-4}$	$4.58\times {10}^{-2}$
		$C_{gg}$	$7.38\times {10}^{-4}$	$2.69\times {10}^{-2}$	$7.96\times {10}^{-4}$	$9.94\times {10}^{-4}$
		$C_{gs}$	$1.10\times {10}^{-4}$	$8.60\times {10}^{-3}$	$1.33\times {10}^{-4}$	$1.62\times {10}^{-2}$
		$g_m/I_d$	$7.33\times {10}^{-4}$	$7.73\times {10}^{-3}$	$5.31\times {10}^{-4}$	$8.60\times {10}^{-4}$
		$g_m{r}_o$	$1.35\times {10}^{-4}$	$1.84\times {10}^{-2}$	$1.57\times {10}^{-4}$	$2.89\times {10}^{-2}$
		$C_{gd}$	$9.54\times {10}^{-4}$	$9.65\times {10}^{-3}$	$1.22\times {10}^{-4}$	$2.68\times {10}^{-2}$
		$C_{dg}$	$9.66\times {10}^{-4}$	$1.47\times {10}^{-2}$	$1.01\times {10}^{-4}$	$1.87\times {10}^{-2}$
		$r_{on}$	$2.62\times {10}^{-4}$	$2.68\times {10}^{-2}$	$2.63\times {10}^{-4}$	$3.64\times {10}^{-2}$
		$C_{dd}$	$7.99\times {10}^{-4}$	$9.20\times {10}^{-3}$	$9.43\times {10}^{-4}$	$1.80\times {10}^{-2}$
	PMOS	$I_d$	$1.91\times {10}^{-3}$	$1.89\times {10}^{-2}$	$2.29\times {10}^{-3}$	$3.26\times {10}^{-2}$
		$V_{th}$	$7.24\times {10}^{-5}$	$1.12\times {10}^{-3}$	$4.04\times {10}^{-5}$	$4.85\times {10}^{-4}$
		$V_{dsat}$	$6.46\times {10}^{-4}$	$7.03\times {10}^{-3}$	$4.53\times {10}^{-4}$	$7.30\times {10}^{-3}$
		$g_m$	$1.73\times {10}^{-3}$	$1.75\times {10}^{-2}$	$2.39\times {10}^{-3}$	$3.64\times {10}^{-2}$
		$f_{ug}$	$1.77\times {10}^{-3}$	$2.01\times {10}^{-2}$	$2.14\times {10}^{-3}$	$2.98\times {10}^{-2}$
		$g_{ds}$	$2.30\times {10}^{-3}$	$2.63\times {10}^{-2}$	$4.35\times {10}^{-3}$	$4.55\times {10}^{-2}$
		$C_{gg}$	$7.10\times {10}^{-4}$	$1.07\times {10}^{-2}$	$7.85\times {10}^{-4}$	$9.67\times {10}^{-3}$
		$C_{gs}$	$1.03\times {10}^{-3}$	$1.53\times {10}^{-2}$	$1.14\times {10}^{-3}$	$1.39\times {10}^{-2}$
		$g_m/I_d$	$6.22\times {10}^{-4}$	$6.99\times {10}^{-3}$	$5.23\times {10}^{-4}$	$7.72\times {10}^{-3}$
		$g_m{r}_o$	$1.53\times {10}^{-3}$	$1.60\times {10}^{-2}$	$1.67\times {10}^{-3}$	$2.29\times {10}^{-2}$
		$C_{gd}$	$6.17\times {10}^{-4}$	$1.02\times {10}^{-2}$	$7.61\times {10}^{-4}$	$1.68\times {10}^{-2}$
		$C_{dg}$	$7.43\times {10}^{-4}$	$9.51\times {10}^{-3}$	$9.93\times {10}^{-4}$	$1.65\times {10}^{-2}$
		$r_{on}$	$2.68\times {10}^{-3}$	$3.25\times {10}^{-2}$	$3.22\times {10}^{-3}$	$3.43\times {10}^{-2}$
		$C_{dd}$	$6.61\times {10}^{-4}$	$9.26\times {10}^{-3}$	$8.50\times {10}^{-4}$	$1.59\times {10}^{-2}$
T40	NMOS	$I_d$	$1.72\times {10}^{-3}$	$1.62\times {10}^{-2}$	$2.46\times {10}^{-3}$	$3.91\times {10}^{-2}$
		$V_{th}$	$8.92\times {10}^{-5}$	$1.13\times {10}^{-3}$	$5.90\times {10}^{-5}$	$6.39\times {10}^{-4}$
		$V_{dsat}$	$6.61\times {10}^{-4}$	$8.12\times {10}^{-3}$	$6.25\times {10}^{-4}$	$7.35\times {10}^{-3}$
		$g_m$	$1.48\times {10}^{-3}$	$1.57\times {10}^{-2}$	$2.15\times {10}^{-3}$	$3.35\times {10}^{-2}$
		$f_{ug}$	$1.53\times {10}^{-3}$	$1.80\times {10}^{-2}$	$2.65\times {10}^{-3}$	$2.86\times {10}^{-2}$
		$g_{d}s$	$1.76\times {10}^{-3}$	$1.98\times {10}^{-2}$	$3.04\times {10}^{-3}$	$6.04\times {10}^{-2}$
		$C_{gg}$	$6.74\times {10}^{-4}$	$8.03\times {10}^{-3}$	$7.39\times {10}^{-4}$	$9.37\times {10}^{-3}$
		$C_{gs}$	$1.03\times {10}^{-3}$	$1.73\times {10}^{-2}$	$1.52\times {10}^{-3}$	$3.20\times {10}^{-2}$
		$g_m/I_d$	$6.57\times {10}^{-4}$	$7.19\times {10}^{-3}$	$5.49\times {10}^{-4}$	$7.27\times {10}^{-3}$
		$g_m{r}_o$	$1.12\times {10}^{-3}$	$1.60\times {10}^{-2}$	$1.31\times {10}^{-3}$	$3.06\times {10}^{-2}$
		$C_{gd}$	$9.28\times {10}^{-4}$	$1.31\times {10}^{-2}$	$1.21\times {10}^{-3}$	$1.92\times {10}^{-2}$
		$C_{dg}$	$1.10\times {10}^{-3}$	$1.21\times {10}^{-2}$	$1.36\times {10}^{-3}$	$1.99\times {10}^{-2}$
		$r_{on}$	$2.12\times {10}^{-3}$	$2.17\times {10}^{-2}$	$2.91\times {10}^{-3}$	$3.70\times {10}^{-2}$
		$C_{dd}$	$8.67\times {10}^{-4}$	$1.08\times {10}^{-2}$	$9.79\times {10}^{-4}$	$1.90\times {10}^{-2}$
	PMOS	$I_d$	$2.13\times {10}^{-3}$	$2.34\times {10}^{-2}$	$2.32\times {10}^{-3}$	$3.07\times {10}^{-2}$
		$V_{th}$	$1.03\times {10}^{-4}$	$1.32\times {10}^{-3}$	$4.64\times {10}^{-5}$	$5.45\times {10}^{-4}$
		$V_{dsat}$	$8.02\times {10}^{-4}$	$9.22\times {10}^{-3}$	$5.96\times {10}^{-4}$	$7.17\times {10}^{-3}$
		$g_m$	$1.79\times {10}^{-3}$	$2.24\times {10}^{-2}$	$2.40\times {10}^{-3}$	$3.86\times {10}^{-2}$
		$f_{ug}$	$1.98\times {10}^{-3}$	$2.26\times {10}^{-2}$	$2.52\times {10}^{-3}$	$3.21\times {10}^{-2}$
		$g_{d}s$	$2.23\times {10}^{-3}$	$3.09\times {10}^{-2}$	$3.15\times {10}^{-3}$	$4.36\times {10}^{-2}$
		$C_{gg}$	$7.95\times {10}^{-4}$	$8.97\times {10}^{-3}$	$7.93\times {10}^{-4}$	$9.93\times {10}^{-3}$
		$C_{gs}$	$1.22\times {10}^{-3}$	$1.97\times {10}^{-2}$	$1.12\times {10}^{-3}$	$1.84\times {10}^{-2}$
		$g_m/I_d$	$7.55\times {10}^{-4}$	$8.36\times {10}^{-3}$	$5.45\times {10}^{-4}$	$1.54\times {10}^{-2}$
		$g_m{r}_o$	$1.34\times {10}^{-3}$	$2.00\times {10}^{-2}$	$1.60\times {10}^{-3}$	$2.12\times {10}^{-2}$
		$C_{gd}$	$1.12\times {10}^{-3}$	$1.66\times {10}^{-2}$	$1.38\times {10}^{-3}$	$2.40\times {10}^{-2}$
		$C_{dg}$	$1.06\times {10}^{-3}$	$1.53\times {10}^{-2}$	$1.03\times {10}^{-3}$	$1.48\times {10}^{-2}$
		$r_{on}$	$2.68\times {10}^{-3}$	$3.33\times {10}^{-2}$	$2.42\times {10}^{-3}$	$2.75\times {10}^{-2}$
		$C_{dd}$	$9.26\times {10}^{-4}$	$1.34\times {10}^{-2}$	$1.24\times {10}^{-3}$	$1.99\times {10}^{-2}$
T180	NMOS	$I_d$	$1.69\times {10}^{-3}$	$4.27\times {10}^{-2}$	$2.66\times {10}^{-3}$	$2.14\times {10}^{-2}$
		$V_{th}$	$8.98\times {10}^{-5}$	$1.42\times {10}^{-3}$	$5.01\times {10}^{-5}$	$8.74\times {10}^{-4}$
		$V_{dsat}$	$5.56\times {10}^{-4}$	$7.98\times {10}^{-3}$	$3.83\times {10}^{-4}$	$7.76\times {10}^{-3}$
		$g_m$	$1.52\times {10}^{-3}$	$4.14\times {10}^{-2}$	$1.72\times {10}^{-3}$	$2.81\times {10}^{-2}$
		$f_{ug}$	$1.52\times {10}^{-3}$	$4.51\times {10}^{-2}$	$1.41\times {10}^{-3}$	$2.52\times {10}^{-2}$
		$g_{d}s$	$1.93\times {10}^{-3}$	$3.33\times {10}^{-2}$	$2.35\times {10}^{-3}$	$5.03\times {10}^{-2}$
		$C_{gg}$	$4.37\times {10}^{-4}$	$5.89\times {10}^{-3}$	$3.32\times {10}^{-4}$	$5.14\times {10}^{-3}$
		$C_{gs}$	$7.57\times {10}^{-4}$	$1.19\times {10}^{-2}$	$4.97\times {10}^{-4}$	$8.36\times {10}^{-3}$
		$g_m/I_d$	$5.73\times {10}^{-4}$	$9.02\times {10}^{-3}$	$5.29\times {10}^{-4}$	$9.68\times {10}^{-3}$
		$g_m{r}_o$	$1.20\times {10}^{-3}$	$3.22\times {10}^{-2}$	$8.27\times {10}^{-4}$	$2.64\times {10}^{-2}$
		$C_{gd}$	$5.02\times {10}^{-4}$	$1.10\times {10}^{-2}$	$3.16\times {10}^{-4}$	$9.96\times {10}^{-3}$
		$C_{dg}$	$5.53\times {10}^{-4}$	$9.21\times {10}^{-3}$	$3.83\times {10}^{-4}$	$8.28\times {10}^{-3}$
		$r_{on}$	$2.15\times {10}^{-3}$	$5.36\times {10}^{-2}$	$1.18\times {10}^{-3}$	$2.13\times {10}^{-2}$
		$C_{dd}$	$4.30\times {10}^{-4}$	$8.49\times {10}^{-3}$	$3.95\times {10}^{-4}$	$1.03\times {10}^{-2}$
	PMOS	$I_d$	$1.64\times {10}^{-3}$	$2.45\times {10}^{-2}$	$1.84\times {10}^{-3}$	$1.99\times {10}^{-2}$
		$V_{th}$	$6.42\times {10}^{-5}$	$1.06\times {10}^{-3}$	$5.74\times {10}^{-5}$	$4.16\times {10}^{-3}$
		$V_{dsat}$	$4.58\times {10}^{-4}$	$7.05\times {10}^{-3}$	$3.57\times {10}^{-4}$	$7.14\times {10}^{-3}$
		$g_m$	$1.44\times {10}^{-3}$	$2.41\times {10}^{-2}$	$1.68\times {10}^{-3}$	$3.19\times {10}^{-2}$
		$f_{ug}$	$1.46\times {10}^{-3}$	$2.29\times {10}^{-2}$	$1.56\times {10}^{-3}$	$2.23\times {10}^{-2}$
		$g_{d}s$	$1.85\times {10}^{-3}$	$3.43\times {10}^{-2}$	$2.04\times {10}^{-3}$	$5.35\times {10}^{-2}$
		$C_{gg}$	$4.17\times {10}^{-4}$	$7.14\times {10}^{-3}$	$3.36\times {10}^{-4}$	$5.60\times {10}^{-3}$
		$C_{gs}$	$7.25\times {10}^{-4}$	$1.43\times {10}^{-2}$	$4.62\times {10}^{-4}$	$1.03\times {10}^{-2}$
		$g_m/I_d$	$4.70\times {10}^{-4}$	$6.99\times {10}^{-3}$	$2.81\times {10}^{-4}$	$6.01\times {10}^{-3}$
		$g_m{r}_o$	$1.11\times {10}^{-3}$	$2.52\times {10}^{-2}$	$1.04\times {10}^{-3}$	$2.65\times {10}^{-2}$
		$C_{gd}$	$4.82\times {10}^{-4}$	$8.62\times {10}^{-3}$	$2.97\times {10}^{-4}$	$9.75\times {10}^{-3}$
		$C_{dg}$	$5.33\times {10}^{-4}$	$9.33\times {10}^{-3}$	$3.43\times {10}^{-4}$	$6.63\times {10}^{-3}$
		$r_{on}$	$2.00\times {10}^{-3}$	$3.06\times {10}^{-2}$	$1.60\times {10}^{-3}$	$2.37\times {10}^{-2}$
		$C_{dd}$	$3.71\times {10}^{-4}$	$8.56\times {10}^{-3}$	$2.99\times {10}^{-4}$	$8.02\times {10}^{-3}$
S180	NMOS	$I_d$	$1.38\times {10}^{-3}$	$2.26\times {10}^{-2}$	$1.87\times {10}^{-3}$	$2.75\times {10}^{-2}$
		$V_{th}$	$7.59\times {10}^{-5}$	$1.59\times {10}^{-3}$	$2.57\times {10}^{-5}$	$4.14\times {10}^{-4}$
		$V_{dsat}$	$4.24\times {10}^{-4}$	$1.04\times {10}^{-2}$	$8.28\times {10}^{-4}$	$9.80\times {10}^{-3}$
		$g_m$	$1.25\times {10}^{-3}$	$3.08\times {10}^{-2}$	$1.42\times {10}^{-3}$	$2.04\times {10}^{-2}$
		$f_{ug}$	$1.31\times {10}^{-3}$	$2.21\times {10}^{-2}$	$1.84\times {10}^{-3}$	$3.23\times {10}^{-2}$
		$g_{d}s$	$1.75\times {10}^{-3}$	$3.24\times {10}^{-2}$	$1.93\times {10}^{-3}$	$6.85\times {10}^{-2}$
		$C_{gg}$	$3.63\times {10}^{-4}$	$6.87\times {10}^{-3}$	$4.70\times {10}^{-4}$	$1.65\times {10}^{-2}$
		$C_{gs}$	$5.71\times {10}^{-4}$	$1.06\times {10}^{-2}$	$3.97\times {10}^{-4}$	$7.04\times {10}^{-3}$
		$g_m/I_d$	$4.82\times {10}^{-4}$	$9.93\times {10}^{-3}$	$2.96\times {10}^{-4}$	$1.25\times {10}^{-2}$
		$g_m{r}_o$	$1.18\times {10}^{-3}$	$2.79\times {10}^{-2}$	$9.21\times {10}^{-4}$	$3.36\times {10}^{-2}$
		$C_{gd}$	$5.32\times {10}^{-4}$	$8.74\times {10}^{-3}$	$4.42\times {10}^{-4}$	$1.07\times {10}^{-2}$
		$C_{dg}$	$4.85\times {10}^{-4}$	$8.41\times {10}^{-3}$	$5.72\times {10}^{-4}$	$1.88\times {10}^{-2}$
		$r_{on}$	$1.92\times {10}^{-3}$	$2.97\times {10}^{-2}$	$1.56\times {10}^{-3}$	$3.47\times {10}^{-2}$
		$C_{dd}$	$3.38\times {10}^{-4}$	$6.28\times {10}^{-3}$	$2.85\times {10}^{-4}$	$7.34\times {10}^{-3}$
	PMOS	$I_d$	$1.41\times {10}^{-3}$	$2.32\times {10}^{-2}$	$1.32\times {10}^{-3}$	$2.30\times {10}^{-2}$
		$V_{th}$	$6.94\times {10}^{-5}$	$1.16\times {10}^{-3}$	$3.47\times {10}^{-5}$	$6.92\times {10}^{-4}$
		$V_{dsat}$	$4.41\times {10}^{-4}$	$6.61\times {10}^{-3}$	$1.86\times {10}^{-4}$	$3.25\times {10}^{-3}$
		$g_m$	$1.29\times {10}^{-3}$	$2.36\times {10}^{-2}$	$1.52\times {10}^{-3}$	$2.69\times {10}^{-2}$
		$f_{ug}$	$1.30\times {10}^{-3}$	$2.36\times {10}^{-2}$	$1.13\times {10}^{-3}$	$3.09\times {10}^{-2}$
		$g_{d}s$	$1.57\times {10}^{-3}$	$3.14\times {10}^{-2}$	$2.71\times {10}^{-3}$	$4.40\times {10}^{-2}$
		$C_{gg}$	$3.60\times {10}^{-4}$	$6.69\times {10}^{-3}$	$3.59\times {10}^{-4}$	$7.58\times {10}^{-3}$
		$C_{gs}$	$6.18\times {10}^{-4}$	$8.84\times {10}^{-3}$	$4.28\times {10}^{-4}$	$6.85\times {10}^{-3}$
		$g_m/I_d$	$4.41\times {10}^{-4}$	$7.18\times {10}^{-3}$	$7.28\times {10}^{-4}$	$2.22\times {10}^{-2}$
		$g_m{r}_o$	$1.03\times {10}^{-3}$	$2.34\times {10}^{-2}$	$8.41\times {10}^{-4}$	$1.85\times {10}^{-2}$
		$C_{gd}$	$4.91\times {10}^{-4}$	$7.96\times {10}^{-3}$	$5.58\times {10}^{-4}$	$2.08\times {10}^{-2}$
		$C_{dg}$	$4.98\times {10}^{-4}$	$7.12\times {10}^{-3}$	$6.03\times {10}^{-4}$	$1.42\times {10}^{-2}$
		$r_{on}$	$1.82\times {10}^{-3}$	$3.56\times {10}^{-2}$	$1.28\times {10}^{-3}$	$3.96\times {10}^{-2}$
		$C_{dd}$	$3.40\times {10}^{-4}$	$5.77\times {10}^{-3}$	$2.28\times {10}^{-4}$	$9.01\times {10}^{-3}$

presents the MAPE and MRE results for all parameters of both the multi-output DNN and single-output DNN models across all PDKs. Overall, the prediction accuracy of the multi-output DNN models is comparable to that of the single-output DNN models. However, the multi-output DNN models demonstrate a distinct advantage in terms of storage space occupation, particularly in addressing the issue of large storage space consumption associated with lookup tables. The multi-output DNN models occupy a smaller storage space, making it more advantageous in mitigating the problem of substantial storage space occupation.

5.1.2. The Comparison to the LUTs

From the analysis of model size, the DNN models, including both NMOS and PMOS for each PDK, are 4.32 MB space. This size is significantly smaller compared to the storage space occupied by LUTs, which amounts to 1.4 GB space for T40 and T65, and 4.4 GB space for T180 and S180. The reduction rates in storage space achieved by the DNN models are 99.69% and 99.90%, respectively. In terms of prediction time analysis in

Table 10. The comparison of time performance between LUTs and DNN models.

Scale of Data (The Exponent of 10)	Time (s)
	DNN Models	LUTs
0	0.00081	0.00132
1	0.00366	0.00113
2	0.00747	0.00169
3	0.05834	0.00487
4	0.29765	0.03070

, the average time consumed for a prediction by the LUTs is 0.00132 s, while the average prediction time for the DNN models is 0.00081 s. However, it is important to note that the DNN models predict 14 parameters, whereas the LUTs only have one parameter. When the time consumption is adjusted to account for all 14 prediction parameters, the DNN models reduce the time overhead by 95.62%. This clearly demonstrates the significant advantages of the DNN models in terms of speed.

Moreover, to validate the accuracy of the DNN models, we conducted out-of-sample testing and compared its performance with that of the LUTs as well as the HSPICE (a simulator from Synopsys) results. Figure 4, Figure 5, Figure 6 and Figure 7 depict the accuracy of the DNN models in predicting the transistor parameters, specifically focusing on the parameters $g_m$ and $I_d$ for each technology. For the sake of simplicity, we present the results for these two parameters only. In the center subfigures, a comparison is made between the predictions of the DNN models and the LUTs, both of which are juxtaposed with the HSPICE results. On the other hand, the right subfigures illustrate the absolute percentage error of the DNN models and the LUTs relative to the HSPICE results. By analyzing the percentage error comparison, it is evident that the DNN models exhibit a maximum percentage error of less than 2% and an absolute average percentage error of approximately 1%. These results highlight the superior performance of the DNN models over the LUTs, which rely on linear interpolation, particularly in terms of the average percentage error in parameter prediction. Furthermore, the percentage error curves of the LUTs demonstrate a sawtooth pattern with gradually decreasing peak values in regions where the parameter value changes significantly. In contrast, the percentage error curve of the DNN models exhibits less fluctuation and greater randomness, indicating its more stable prediction performance.

5.2. Circuit Migration Design

5.2.1. Folded Cascode Operation Amplifier (FC OPAMP)

The FC OPAMP is shown in Figure 8.

Table 11. Specification for FC OPAMP in T40, T65, T180, and S180 technologies.

Parameter	Unit	Specification (T40 and T65)	Specification (T180 and S180)
$V_{DD}$	V	1.2	1.8
$C_L$	pF	5	2
DC loop gain ($A_0$)	dB	≥55	≥65
Gain-band width ($GBW$)	MHz	≥ 20	≥50
Phase margin ($PM$)	${}^{\circ }$	≥60	≥60
Common mode rejection ratio ($CMRR$)	dB	≥70	≥80
Slew rate ($SR$)	V/us	≥ 10	≥20
Area	µm${}^2$	minimum	minimum

presents the specification requirements of FC OPAMP for T40, T65, T180, and S180. Equation (2) shows the design equations of the FC OPAMP, while

Table 12. The design variable of each transistor in FC OPAMP.

Parameter	Unit	Min	Max
${(g_m/I_d)}_0$	S/A	10	15
${(g_m/I_d)}_{1,2}$	S/A	15	27
${(g_m/I_d)}_{3,4}$	S/A	12	17
${(g_m/I_d)}_{5,6}$	S/A	12	17
${(g_m/I_d)}_{7,8}$	S/A	12	17
${(g_m/I_d)}_{9,10}$	S/A	12	17
L	µm	0.5	2.5

provides the range of each transistor design variable for the FC OPAMP. For this specific example, the value of $V_{dsmarg}$ is set at 50 mV, while the value of $\beta$ is set to 1.05.

In this case, by employing DNN models for circuit design, the database comprising approximately 780,000 design points requires approximately 92 s for generation for each technology, whereas the utilization of LUTs necessitates approximately 155 s. Compared with using LUTs, using DNN models can shorten the time consumption by 40.65%. This implies that in practical design applications, DNN models are still capable of maintaining a speed advantage.

Table 13. List of device sizes of the FC OPAMP.

Parameter	Unit	T40	T65	T180	S180
${(W/L)}_0$	µm/µm	10.4/0.5	37.6/0.5	12.8/0.5	10.4/0.5
${(W/L)}_{1,2}$	µm/µm	112/1.1	84.6/0.5	73/0.8	43/0.8
${(W/L)}_{3,4}$	µm/µm	124/1.1	39.2/0.5	11.2/0.8	4.2/0.8
${(W/L)}_{5,6}$	µm/µm	140.8/1.1	41/0.5	16/0.8	5.8/0.8
${(W/L)}_{7,8}$	µm/µm	30.4/1.1	15.2/0.5	32/0.8	24/0.8
${(W/L)}_{9,10}$	µm/µm	22.8/1.1	10.8/0.5	17.2/0.8	16/0.8

,

Table 14. Pre-simulation results of FC OPAMP.

Parameter	Unit	T40	T65	T180	S180
$A_0$	dB	55.3	59.2	69.5	69.8
$GBW$	MHz	22.6	24.1	53.4	54.5
$PM$	${}^{\circ }$	71.9	85.6	73.6	68.6
$CMRR$	dB	88.6	115.6	103.3	118.5
$SR$	V/us	11.3	13.2	35.1	26.5
area	µm${}^2$	951.2	209.6	243.8	159.1

and

Table 15. Post-simulation results of FC OPAMP.

Parameter	Unit	T40	T65	T180	S180
$A_0$	dB	55.0	58.6	68.2	69.4
$GBW$	MHz	20.9	22.5	51.5	52.1
$PM$	${}^{\circ }$	65.5	83.8	76.8	79.0
$CMRR$	dB	72.1	82.9	93.5	98.1
$SR$	V/µs	10.4	12.5	26.9	24.7

display the sizing results, pre-simulation results, and post-simulation results of the FC OPAMP in T40, T65, T180, and S180, respectively. The results demonstrate two key observations. Firstly, the circuit simulation results in all four technologies meet the specified requirements, validating the effectiveness of the proposed circuit migration design method. Secondly, it is noteworthy that, for comparable simulation outcomes, the transistor size required in T40 exceeds that of T65, while the sizing results between T180 and S180 are more similar. This observation suggests that it is more challenging to realize this circuit in T40.

$$\begin{array}{cc}\hfill & \hfill A_o=\frac{g_{m5}{r}_{o5}{g}_{m7}{r}_{o7}{G}_1}{\beta {\lambda }_9{g}_{m5}{r}_{o5}+g_{m7}{r}_{o7}[(1+\beta ){\lambda }_3+{\lambda }_1]},\hfill \\ \hfill & \hfill CMRR=\frac{\beta A_{o1}{g}_{m0}{r}_{o0}{G}_9}{G_0},\hfill \\ \hfill & \hfill GBW=\frac{g_{m1}}{2\pi (C_L+C_{dd8}+C_{dd6})},\hfill \\ \hfill & \hfill SR=\frac{I_{D0}}{C_c},\hfill \\ \hfill & \hfill {\omega }_{p2}=\frac{g_{m5}}{C_{dd3}+C_{dd1}+C_{ss5}},\hfill \\ \hfill & \hfill PM={90}^{\circ }-\arctan \left(\frac{2\pi GBW}{{\omega }_{p2}}\right),\hfill \end{array}$$

(2)

where G = $g_m/I_d$, $\beta$ = $I_{d5}/I_{d1}$, $\lambda$ = $g_{ds}/I_{ds}$.

5.2.2. Miller Operation Amplifier(MI OPAMP)

The MI OPAMP is shown in Figure 9. The specification requirements of MI OPAMP for T40, T65, T180, and S180 are presented in

Table 16. The specification of MI OPAMP for T40, T65, T180, and S180 technologies.

Parameter	Unit	Specification (T40 and T65)	Specification (T180 and S180)
$V_{DD}$	V	1.2	1.8
$C_L$	pF	5	5
$A_0$	dB	≥60	≥72
$GBW$	MHz	≥25	≥30
$PM$	${}^{\circ }$	≥60	≥60
$CMRR$	dB	≥50	≥70
$SR$	V/us	≥ 10	≥15
area	µm${}^2$	minimum	minimum

. The design equations of the MI OPAMP are provided in Equation (3), while the range of each device design variable for MI OPAMP is specified in

Table 17. The design variable of each device in MI OPAMP.

Parameter	Unit	Min	Max
${(g_m/I_d)}_0$	S/A	10	15
${(g_m/I_d)}_{1,2}$	S/A	15	27
${(g_m/I_d)}_{3,4}$	S/A	10	15
L	µm	0.5	2.5
$C_c$	pF	1	2
$R_z$	$\Omega$	1000	5000

. It is worth noting that the $g_m/I_d$ values of M5, M6, and M7 in the MI OPAMP are influenced by the $V_{gs}$ of M3 and M0, and therefore, there is no need to restrict the $g_m/I_d$ range of M5, M6, and M7. The saturation voltage margin parameter, $V_{dsmarg}$, is set to 50 mV in this particular example.

In the context of this circuit design case, it has been observed that the generation of a database consisting of approximately one million design points through the utilization of the DNN models takes roughly 120 s, whereas the same task requires approximately 210 s when utilizing LUTs. This represents a 42.86% reduction in the time overhead, as compared to the LUTs approach.

Table 18. List of device sizes of the MI OPAMP.

Parameter	Unit	T40	T65	T180	S180
${(W/L)}_0$	µm/µm	17.6/0.5	15/0.5	28/0.5	27/0.5
${(W/L)}_{1,2}$	µm/µm	312/2	82.8/0.5	46/0.5	38.4/0.5
${(W/L)}_{3,4}$	µm/µm	10.4/2.3	1.6/0.5	3.2/0.5	2.7/0.5
${(W/L)}_5$	µm/µm	70/1.4	17.6/0.5	36/0.5	29.4/0.5
${(W/L)}_6$	µm/µm	214.2/2.3	128/1.1	221/0.5	126/0.5
${(W/L)}_7$	µm/µm	4.4/0.5	6/0.5	7/0.5	6/0.5
$C_c$	pF	1.75	1.5	1.5	1.5
$R_z$	k$\Omega$	2	1.6	1.1	1.2

,

Table 19. Pre-simulation results of MI OPAMP.

Parameter	Unit	T40	T65	T180	S180
$A_0$	dB	62.0	64.8	76.0	76.1
$GBW$	MHz	31.8	28.1	32.3	35.1
$PM$	${}^{\circ }$	84.3	64.5	73.2	72.2
$CMRR$	dB	53.5	54.2	77.2	76.9
$SR$	V/us	23.9	14.2	20.8	23.3
area	µm${}^2$	1895.3	241.5	258	132.3

and

Table 20. Post-simulation results of MI OPAMP.

Parameter	Unit	T40	T65	T180	S180
$A_0$	dB	61.5	63.6	75.4	74.9
$GBW$	MHz	29.4	27.7	31.8	33.7
$PM$	°	81.7	64.7	64.7	69.6
$CMRR$	dB	52.9	53.6	75.2	74.5
$SR$	V/µs	21.7	13.8	20.1	22.4

display the sizing results, pre-simulation results, and post-simulation results of the MI OPAMP in T40, T65, T180, and S180, respectively. The results indicate that the circuit simulation results in all four PDKs satisfying the specified requirements, thus demonstrating the effectiveness of the proposed method. Furthermore, consistent with the sizing results of the FC OPAMP, it is observed that the results for T180 and S180 exhibit relatively close values. However, in order to meet the specification requirements, T40 demands larger device sizes and RC values compared to T65.

$$\begin{array}{c}\hfill A_{o1}=\frac{G_1}{{\lambda }_1+{\lambda }_3},\hfill \\ \hfill A_{o2}=\frac{G_5}{{\lambda }_5+{\lambda }_6},\hfill \\ \hfill A_o=A_{o1}·A_{o2},\hfill \\ \hfill CMRR=\frac{A_{o1}{g}_{m0}{r}_{o0}{G}_3}{G_0},\hfill \\ \hfill GBW=\frac{g_{m1}}{2\pi C_c(1+\alpha )},\hfill \\ \hfill SR=min\{\frac{I_{D0}}{C_c},\frac{I_{D6}-I_{D0}}{C_2}\},\hfill \\ \hfill {\omega }_{p2}=-\frac{g_{m5}{C}_c}{C_1{C}_2+C_1{C}_c+C_2{C}_c},\hfill \\ \hfill {\omega }_{p3}=-\frac{1}{R_z{C}_1},\hfill \\ \hfill {\omega }_{z1}=\frac{1}{C_c(\frac{1}{g_{m5}}-R_z)},\hfill \\ \hfill PM={90}^{\circ }-\arctan \left(\frac{2\pi GBW}{{\omega }_{p2}}\right)-\arctan \left(\frac{2\pi GBW}{{\omega }_{p2}}\right)+-\arctan \left(\frac{2\pi GBW}{{\omega }_{z1}}\right),\hfill \end{array}$$

(3)

where $\alpha =\frac{1+\frac{C_1}{C_c}}{A_{o2}}+\frac{1+\frac{C_2}{C_c}}{\frac{g_{m5}}{g_{m1}}{A}_{o1}}$, $C_1$=$C_{dd2}+C_{dd4}+C_{gs5}$, $C_2$ = $C_{dd6}+C_{db5}+C_L$.

6. Conclusions

This paper presents a novel approach for training DNN models to replace the LUTs in the $g_m/I_d$ method, thereby significantly reducing storage space requirements. The proposed method focuses on training DNN models for NMOS and PMOS device parameters in prevalent IC design technologies, namely T40, T65, T180, and S180. By employing DNN models, the storage space requirements can be reduced by at least 99% compared to LUTs. Furthermore, the DNN models demonstrate high prediction accuracy, with an average percentage error of less than 1%. In terms of prediction time, the DNN models outperform LUTs by reducing the time overhead by 91.46% when predicting an equivalent number of parameters.

Additionally, this paper introduces an automated porting design approach for analog circuits that combines the DNN models with the $g_m/I_d$ design method. The objective is to facilitate circuit design reuse across different technologies. The proposed method is validated through migration design experiments involving folded cascode amplifiers and Miller two-stage amplifiers in the mainstream technologies of T40, T65, T180, and S180. The experimental results demonstrate that utilizing the DNN models can reduce the time overhead by 40% compared to using LUTs. Furthermore, the pre- and post-simulation results of the circuit confirm that the proposed method enables the automated design of circuits with identical specifications across different technologies.

Based on the experimental results, it was observed that to achieve the same performance specifications, the sizing of operational amplifiers in T40 technology is relatively larger than that of T65 technology for both circuit architectures. Therefore, it is recommended that for advanced technology circuit design, the performance targets can be relaxed to obtain smaller circuit sizes. Alternatively, one may consider replacing the architecture to meet the desired specifications.