A Low-Voltage Class-D VCO with Implicit Common-Mode Resonator Implemented in 55 nm CMOS Technology

Abstract

This paper presents a Class-D voltage-controlled oscillator (VCO) with a hybrid switch capacitor array. In order to reduce the phase noise of the oscillator, an implicit common-mode resonance technique is used, effectively suppressing the conversion of power supply noise to VCO phase noise. At the same time, due to the use of a transformer in implicit common-mode resonance technology, the core area of the oscillator is not significantly increased compared with the traditional Class-D VCO. Based on the proposed technology, the proposed VCO exhibits lower phase noise compared to the original Class-D VCO, and also has many different advantages compared to low-voltage VCOs produced by similar technological processes. The proposed VCO was designed in a 55 nm CMOS process. Simulation results show that this VCO has an operating range from 4.36 to 6.43 GHz, resulting in the frequency tuning range (FTR) of 38.5%. In addition, its power consumption was 3.46 mW, the phase noise at 4.36 GHz was −124.2 dBc/Hz@1 MHz, and the figure of merit (FoM) was −191.6 dBc/Hz@1 MHz. The core area is 0.15 mm².

1. Introduction

Phase noise characteristics as core indicators of the voltage-controlled oscillator (VCO) and the phase-locked loop (PLL) directly reflect the quality of the frequency source output signal, which directly affects the frequency conversion function in wireless transceivers. To provide an excellent local oscillation signal for a wireless transceiver [1], various improved topological structures, such as Class-C [2], Class-D [3] and Class-F VCOs [4], have been continually proposed as the core module of PLL frequency synthesizer.

With continuous improvement of the technology, ensuring the safe operation of nanoscale devices and lower the direct current (DC) power consumption, the gradually decreasing operating voltage of wireless transceivers has become an intriguing trend, requiring an high-performance oscillator topology that can operate at low voltage. This paper focuses on the Class-D VCO topology, which has significant advantages when operating at low supply voltages.

The phase noise ${Ł}_{(\Delta w)}$ generated by the oscillator itself is shown in Formula (1) [5,6], where K is the Boltzmann constant, T is the absolute temperature, $R_p$ is the parasitic equivalent parallel resistance, $C_{w_0}$ is the capacitance at frequency $w_0$, and $\Delta w$ is the offset frequency. It can be seen that the mentioned phase noise is inversely proportional to the peak Vmax of the oscillator output waveform. The peak voltage of a traditional Class-B VCO is generally twice the supply voltage (2VDD), leading to a decrease in the peak value of the oscillator waveform at low voltage, further worsening the phase noise.

$${Ł}_{(\Delta w)}=10·log10[\frac{1}{2}·\frac{kT}{V_{max}^2}·\frac{1}{R_p·{\left(C_{w_0}\right)}^2}·{\left(\frac{w_0}{\Delta w}\right)}^2]$$

(1)

In the derivation of [3], the peak voltage of a Class-D VCO can be more than three times that of the power supply voltage, as shown in Figure 1, which means that the peak voltage of a Class-D VCO exceeds at least one VDD of a Class-B under the same power supply voltage, greatly reducing the phase noise generation of the oscillator itself.

On the other hand, compared to a traditional Class-B VCO [7], a Class-D VCO abandons the current source driving method, thus eliminating some noise sources and making a well-optimized Class-D VCO with better phase noise performance at the same power consumption.

The effect of power supply on the phase noise of oscillators has been discovered and studied by designers for a long time. In addition to the huge difference in peak voltage between Class-D and Class-B VCOs, the output waveform of a Class-D VCO differs from the standard sinusoidal waveform in that the waveform is near a step. As seen in [5], if the oscillating wave is square, the impulse sensitivity function (ISF) value can be ignored in the time span due to the zero derivative of the oscillating voltage, resulting in that even injecting noise into the LC tank cannot change the phase of the oscillating wave. Theoretically, we realize that the closer the output waveform is to the square wave, the more difficult it is to transform the noise in the power supply into phase noise. Therefore, the closer the waveform of the oscillator is to the square wave, the lower the proportion of noise in the power supply is converted to phase noise, which is the design principle of Class-F VCOs [4]. By adding inductance to produce a third harmonic, the final output first harmonic is mixed with the third harmonic to produce an output waveform that approaches the square wave’s. In [8], understanding the mechanism of phase noise suggests that even harmonics, especially second harmonics, are the main source of power supply output phase noise. This also suggests that adding an LC tank in the oscillator structure can filter out the second harmonic, effectively improving the phase noise performance of the VCO. However, the increase in additional inductance greatly increases the area of the VCO. The implicit common-mode resonance technology in [9] replaces a single inductance with a transformer, making the common-mode resonance at the second harmonic of the output frequency, saving space while maintaining the original resonance function.

Compared to Class-B VCO LC tanks, Class-D VCO LC tanks present greater challenges for designers. For example, for Class-B VCOs, if the equivalent capacitance values at both ends of the output are the same, whether they are floating capacitors or single-ended capacitors will not affect the frequency of the output waveform or the phase noise. However, the time-varying characteristics of the LC tank for Class-D VCOs require additional efforts in the selection of capacitance type; otherwise, its phase noise performance is lower than that of Class-B VCOs. Therefore, the switched capacitor array based on the floating capacitor in Class-B VCOs cannot be directly used in Class-D VCOs, and its switched capacitor array needs to be redesigned.

Based on the above issues and analysis, this paper presents the further suppression of phase noise deterioration by implicit common-mode resonance technology for Class-D VCOs operating at low voltage. In the Section 2, the design details of the hybrid switched capacitor array with a Class-D VCO and common-mode resonance technology are introduced. Under the given coupling coefficients, the switched capacitor structure is found to produce the best phase noise performance. The Section 3 shows the technical specifications of the Class-D VCO with implicit common-mode resonance technology and compares them with VCOs operating at low voltages in a similar technological process. The Section 4 summarises this article.

2. Implemented Circuits

Figure 2 shows the basic structure block diagram of a Class-D VCO with common-mode resonance, mainly divided into the switch, transformer, and hybrid switched capacitor array.

2.1. Class-D VCO

Figure 3 presents the topological structure of traditional Class-B and Class-D VCOs. The tail current source, usually a transistor, occupies a voltage drop that directly limits the amplitude of the output waveform. The output amplitude of a Class-B VCO is generally (2VDD-VS), meaning that the output amplitude of the oscillator is greatly affected at low voltage, and a decrease in amplitude can also affect the performance of the oscillator’s phase noise. Meanwhile, the tail current source is also an another source of phase noise in addition to the LC tank and cross-coupled pair, resulting in the output signal quality of a traditional Class-B VCO that cannot match the requirements of modern mobile communications for signal phase noise.

To satisfy that the oscillator can still output high-quality oscillator waveforms at low voltage, we focus on the Class-D oscillator topology [10,11,12]. Compared with a traditional Class-B oscillator, Class-D VCOs remove the tail current source and replace the transistors of the original cross-coupled transistors with two larger high-quality switch transistors. Since the original transistor is replaced by a high-quality switch, the power dissipated on it is almost zero, causing power dissipation of the oscillator to occur on the LC tank of the oscillator. This means that the power utilization efficiency of the Class-D oscillator is much higher than the Class-B oscillator. Meanwhile, this change significantly improves the output amplitude of the oscillator, enables the peak value to reach 3VDD, and the higher amplitude can reduce the phase noise. Therefore, the proposed Class-D oscillator has unique advantages in low power consumption and phase noise driven by low voltages, as it does not require an additional driving current source and eliminates potential sources of phase noise.

However, as previously mentioned, the modified bottom differential pair of a Class-B VCO produces new characteristics in the phase noise of Class-D VCOs due to the difference in flow paths between floating and single-ended capacitors on the current, as shown in Figure 4.

This difference causes the phase noise to change as shown in Formulas (2) and (3), where $K_B$ is the Boltzmann constant, T denotes the absolute temperature, $R_c$ and $R_L$ represent the parasitic resistance of capacitors and inductors, respectively, and $n_{MOS}$ is normalized from the noise generated by switches to the noise in the LC tank.

$${Ł}_{C_{float}}(\Delta w)=10·log10[\frac{k_{B}T}{V_{DD}^2}·(0.104R_L+0.141R_C)·{\left(\frac{w_{float}}{\Delta w}\right)}^2·(1+n_{MOS})]$$

(2)

$${Ł}_{C_{se}}(\Delta w)=10·log10[\frac{k_{B}T}{V_{DD}^2}·(0.104R_L+\frac{0.141}{2}{R}_C)·{\left(\frac{w_{se}}{\Delta w}\right)}^2·(1+n_{MOS})]$$

(3)

From the above formulas, it can be seen that the phase noise of the Class-D oscillator deteriorated with the introduction of a large number of floating capacitors. In [3], the author determined that a special ratio X with a floating capacitor and a single terminal capacitor optimizes the phase noise characteristics of the Class-D oscillator by scanning the capacitance ratio. However, the inherent principle of this kind of oscillator is not deduced. We will further explain this problem in the following introduction to common-mode resonance technology.

2.2. Common-Mode Resonance

2.2.1. Explicit and Implicit Common-Mode Resonance Technology

By analysing the physical mechanism of the phase noise, we can see that even harmonics at the power supply are the main source of the oscillator phase noise. The second harmonic can easily down-converted to near the output frequency, so nearly half the noise in the second harmonic can affect the performance of the output phase noise. To optimize the phase noise, we provide a high impedance at the second harmonic to prevent the noise at the second harmonic from being loaded into the LC tank by differential pairs [13,14]. Therefore, one of the most common methods is to directly provide a high-resistance resonator at the output second harmonic on the source pole of the cross-coupled transistor, also known as explicit common-mode resonance, as shown in Figure 5. The simulation in [8] shows that the increase in the resonator can significantly improve the phase noise of the oscillator, but the area of the VCO inevitably increases because of the additional capacitance and inductance.

Explicit common-mode resonance validates the significant enhancement effect of common-mode resonance theory on oscillator phase noise, but it requires additional area, contrary to the small area pursued by Class-D VCOs. Therefore, implicit common-mode resonance is adopted, as shown in Figure 6a. We replace a single inductive coil with a pair of transformers, with capacitors divided into single-ended and floating capacitors. As shown in Figure 6b, we can see the differences in the flow paths of differential- and common-mode signals. For differential-mode signals, the equivalent capacitance of the resonator includes a single-ended capacitor and a floating capacitor, but for common-mode signals, the floating capacitor is shorted due to the consistent potential at both ends, and the equivalent capacitance of the resonator is only a single-ended capacitor. Therefore, the two different paths through which common- and differential-mode signals flow generate high impedance at the two frequencies $F_{CM}$ and $F_{DM}$, respectively. We only need to control the common-mode resonance at the second harmonic of the differential mode to complete the noise filtering at the second harmonic.

The differential-mode $C_{DM}$ and common-mode $C_{CM}$ equivalent capacitance is as (4) and (5), respectively. By choosing the appropriate transformer-coupling factor K and the ratio X of the floating to single-end capacitance, the common-mode resonance can be achieved at the desired frequency.

$$C_{DM}=C_{se}+C_{fl}$$

(4)

$$C_{CM}=C_{se}$$

(5)

2.2.2. Hybrid Capacitor Array Design

When the transformer-coupling factor K is first determined, the oscillation frequency $w_{DM}$ of the differential-mode signal and the common-mode resonance frequency $w_{CM}$ are as (6) and (7), respectively, where $C_{fl}$ is the floating capacitor and $C_{se}$ is the single-ended capacitor.

$$w_{DM}=\frac{1}{\sqrt{(1+k)L(C_{fl}+C_{se})}}$$

(6)

$$w_{CM}=\frac{1}{\sqrt{(1-k)L{C}_{se}}}$$

(7)

Since the common-mode resonance frequency needs to be set at the second harmonic of the oscillator frequency, we obtain the ratio X between the floating capacitance and the single-ended capacitance in the oscillator, as shown in the Formula (9).

$$w_{CM}=2\ast w_{DM}$$

(8)

$$X=\frac{C_{fl}}{C_{se}}=\frac{3-5k}{1+k}$$

(9)

To verify the correctness of the implicit common-mode resonance theory, the total capacitance at the output of the oscillator is kept constant, and the ratio n between the two is scanned, as shown in Figure 7a. The relationship between the oscillator phase noise and the variable n is illustrated in Figure 7b. It is worth mentioning that to avoid the influence of parasitic transistor capacitance, we chose the ideal transistors without parasitic parameters for the simulation. It can be seen that the influence of different capacitance ratios on the phase noise of the oscillator is verified in the implicit common-mode resonance theory.

In addition to the requirement of common-mode resonance technology for capacitance type, we can see that the Class-D VCO itself has an important impact on the capacitance type due to its current path. Through analysis, it can be seen that the noise suppression at the second harmonic is caused by the secondary resonator. Therefore, it can be seen that the capacitance structure has a very important impact on the phase noise optimization of this type of oscillator. The mismatch of the capacitance ratio may even cause a sharp deterioration of the phase noise of the oscillator.

Therefore, traditional switching capacitor arrays need to be rebuilt. As shown in Figure 8a, we can see that the traditional switching capacitor is a floating capacitor. Therefore, we need to replace it with a hybrid switching capacitor array that contains both floating and single-ended capacitors after being switched on. The units are shown in Figure 8b. In addition, the ratio X of the floating to single-end capacitance and the coupling factor K also need to be considered together. Because there is a certain amount of parasitic capacitance in the circuit that needs to be carefully considered, a too large a difference between the floating capacitance and single-ended capacitance often results in the parasitic capacitance itself exceeding the optimal ratio X. To accommodate the design and account for the parasitic capacitance in the layout, we set the ratio X to 1, so the coupling coefficient of the transformer is $\frac{1}{3}$, which is easier to implement.

After the specific range of capacitance values is theoretically determined, the ratio of the actual capacitance further deviates from the ideal value guided by the common-mode resonance theory due to the influence of parasitic capacitance introduced by the large number of transistors and layers of metal wires in the layout. Further scanning near the ideal capacitance ratio determines the ratio of the final hybrid switched capacitor array.

2.3. Complete Circuit Implementation

The complete circuit mainly consists of transformers, hybrid switched capacitor arrays, variable capacitors and switch pairs consisting of multiple transistors, as shown in Figure 9.

The hybrid switched capacitor array consists of a 4-bit floating capacitor array and a 4-bit single-ended capacitor array. Each switch acts on both capacitors simultaneously to ensure that the equivalent floating capacitance and single-ended capacitance at each switch state are near the designed target ratio.

It is worth noting that a variable capacitor connected as a fixed potential at one end can also be considered a single-end capacitor, so a pair of floating capacitors needs to be added as a supplement to the design. Since the capacitance of the variable capacitor changes and its corresponding floating capacitor is a fixed capacitor, the optimal ratio always deviates during the process of adjusting the tuning voltage (VT), resulting in phase noise deterioration. The rate of change in the variable capacitance is directly proportional to the tuning range of the entire VCO. The excessive rate of change also increases the offset of the capacitance ratio. Due to this phenomenon, the tuning range of an oscillator using common-mode resonance technology needs to be compromised with the phase noise.

3. Simulation Results

The Class-D VCO with phase noise optimization using implicit common-mode resonance technology is introduced in this paper based on the SMIC-55 nm process. The layout design is shown in Figure 10. The main structure is divided into transformer modules for implicit common-mode resonance, a hybrid switching capacitor array with floating capacitance and single-ended capacitance, and cross-coupled pairs of multiple MOSFET used as switches, with a total area of 0.15 mm². As a VCO designed for low-voltage environments, the circuit can operate at voltages as low as 0.5 V with a total power consumption of 3.46 mW. The lower power supply voltage deteriorates the phase noise generation of the oscillator. By introducing the common-mode resonance technology, the designed VCO can maintain a good phase noise performance at low voltages and low power consumption, and its optimal and worst phase noise characteristic curves are shown in Figure 11a.

Based on the simulation results of the layout, the tuning range of the proposed VCO is from 4.36 to 6.43 GHz, and the tuning range (TR) value is 38.46%, as shown in Figure 11b. At an offset frequency of 1 MHz, the optimal phase noise performance is −124.2 dBc/Hz. According to the calculation formula of the figure of merit ($FoM$) (10) and $Fo{M}_T$ (11), the best FoM and FoMT for this VCO are 191.6 dBc/Hz and 203.3 dBc/Hz, respectively.

$$FoM=-PN+20{log}_{10}\left(\frac{f_0}{\Delta f}\right)-10{log}_{10}\left(\frac{P_{DC}}{1\mathrm{mW}}\right)$$

(10)

$$Fo{M}_T=-PN+20{log}_{10}\left(\frac{f_0}{\Delta f}\right)-10{log}_{10}\left(\frac{P_{DC}}{1\mathrm{mW}}\right)+20{log}_{10}\left(\frac{TR[\%]}{10}\right)$$

(11)

The central power end of a traditional transformer leads to the introduction of longer metal interconnects between the transformer and the power pad, resulting in parasitic capacitance and inductance that are difficult to quantify. Therefore, traditional transformers make it more difficult to design and match our capacitors. Considering the layout symmetry and parasitic parameters, the power ends of the two inductances of the transformer are pulled out to both sides. The three-dimensional (3D) view of the transformer without the patterned ground shield (PGS) used in the final design is shown in Figure 12. The advantage of this structure is that by placing the power supply pad symmetrically on both ends of the transformer the reduction in the length of the metal interconnect greatly reduces the parasitic capacitance and inductance, while the symmetry on the layout results in the symmetry of the parasitic parameter sizes, helpful in reducing the mismatch between the two inductance of the transformer.

An EMX simulation was performed from 0 to 60 GHz on the proposed transformer. The inductance values L and quality factor Q of the two inductors L1 and L2 of the transformer are shown in Figure 13.

The EMX simulation shows that the quality factor of each inductance of the transformer fluctuates between 20 and 26 during the tuning frequency, and the mismatch between the two inductances is less than 0.3%. Low matching error between L1 and L2 ensures that high impedance can be accurately generated at the second harmonic of the output signal.

To demonstrate this combination’s performance improvement for the VCO at low voltage, a comparison of Cthe lass-D VCO performance for low-voltage environments is shown in

Table 1. Performance comparison of recently published low-voltage VCOs.

TIME	JSSC’13		JSSC’16		ISSCC’21	ISSCL’22		This Work
	[3]		[14]		[13]	[12]
Toplogy	Class-D		Class-D/F2		F2 ind. + Head	Class-D w/PTV		Class-D +
	Tail Filter				Resonator	Ind.		Resonator
tech.	65 nm CMOS		40 nm CMOS		65 nm CMOS	65 nm CMOS		55 nm CMOS
VDD (V)	0.4		0.5		0.4	0.35		0.5
Tuning Range (GHz)	3.0–4.8		3.3–4.5		5.0–6.36	3.67–4.44		4.36–6.43
(%)	45		31		23.9	18.7		38.5
Frequency (GHz)	3.0	4.8	3.3	4.5	6.36	3.68	4.44	4.36	6.43
Power (mW)	6.8	3.6	4.1	2.5	3.36	4.95	4.2	3.46	3.46
PN@1 MHz (dBc/Hz)	−128	−121	−123.4	−119	−125	−129.1	−124.8	−124.2	−119.5
FoM@1 MHz (dBc/Hz)	189.2	189.1	187.6	188	195.8	193.5	191.4	191.6	190.2
FoMT@1 MHz (dBc/Hz)	202.3	202.2	197.4	197.8	202.6	198.9	196.8	203.3	201.9
Core Area (mm2)	0.15		0.15		0.43	0.12		0.15

. In order to compare the common-mode resonance technology to optimize the performance of the VCO phase noise, we chose a similar process to compare the performance of the VCO (the minimum MOS gate width in the 55 nm CMOS process is 60 nm as in the 65 nm CMOS process).

It can be seen that the addition of the common mode resonator further reduces the phase noise of the Class-D VCO compared with [3]; however, the tuning range of the circuit is slightly lower than that of a typical Class-D VCO to maintain a more accurate common-mode resonance frequency. However, due to the lower power consumption of the circuit at low voltage, the $FoM$ and $Fo{M}_T$ of the design are slightly better than the traditional Class-D VCO.

The idea of phase noise optimization in [14] is directional optimization for 1/f noise [15]. Designers are also aware of the different effects of different capacitors on common-mode second harmonics. From the basic concept of phase noise, the closer the output waveform is to the square wave, the lower the proportion of noise is converted to phase noise at the power source. This is also the basic logic of the phase noise optimization technology for Class-F VCOs, making the output from the original sine wave to the square wave by increasing the third harmonic. According to the performance comparison, it can be seen that the phase noise of the Class-D VCO using common-mode resonance technology is similar to that of a Class-D/F2 VCO. This may be due to the fact that the waveform of a Class-D VCO using high-quality switches is closer to a square wave compared to traditional sine waves.

Further use of second-harmonic suppression technology and third-harmonic technology in [13] results in an excellent phase noise performance in its design. However, due to the large use of its multi-peak resonance technology for inductance, the design of the circuit structure is more complex and the area is multiplied compared with the design in this paper. At the same time, its tuning range is slightly lower than the design in this paper. Compared with the design in [12,16], the phase noise around 4.5 GHz is similar. The tuning range and power consumption of the design in this paper are both better than those in [12], whose disadvantage is that a larger chip area is used.

4. Conclusions

In this paper, based on a Class-D VCO, we built an oscillator with a small area, good phase noise performance, and a wide tuning range at low voltage and low power consumption by using common-mode resonance technology. Due to the difference in oscillation mode between Class-D and Class-B VCOs, the influence of the floating capacitance and single-ended capacitance ratio on the phase noise performance of the Class-D VCO was hampering the use of a Class-D VCO. For implicit common-mode resonance technology, the tuning range falls victim to phase noise optimization. In implicit common-mode resonance technology, the ratio of floating capacitance to single-ended capacitance has a common internal mechanism for the effect of phase noise of the Class-D oscillator described above. Therefore, the Class-D oscillator with implicit common-mode resonance not only retains the good characteristics of low power consumption under low power supply voltage operation but also improves the phase noise due to the suppression of second harmonic noise by the equivalent common-mode resonator. Fabricated using the SMIC 55 nm CMOS process, the voltage-controlled oscillator proposed in this paper has a tuning range from 4.36 to 6.43 GHz with a TR value of 38.46%. At an offset frequency of 1 MHz, the optimal phase noise performance is −124.2 dBc/Hz, the FoM value is 191.6 dBc/Hz, and the FoMT value is 203.3 dBc/Hz. The voltage-controlled oscillator has an area of 0.15 mm² and consumes approximately 3.46 mW at a power voltage of 0.5 V.