Effect of P+ Source Pattern in 4H-SiC Trench-Gate MOSFETs on Low Specific On-Resistance
1
Department of Electrical Engineering, Pusan National University, Busan 46241, Republic of Korea
2
School of Electronic Engineering, Kumoh National Institute of Technology, Gumi 39177, Republic of Korea
*
Authors to whom correspondence should be addressed.
Appl. Sci. 2023, 13(1), 107; https://doi.org/10.3390/app13010107
Submission received: 28 November 2022
/
Revised: 14 December 2022
/
Accepted: 19 December 2022
/
Published: 22 December 2022
(This article belongs to the Section Electrical, Electronics and Communications Engineering)
Abstract
:Novel 1.7-kV 4H-SiC trench-gate MOSFETs (TMOSFETs) with a grid pattern and a smaller specific on-resistance are proposed and demonstrated via numerical simulations. The proposed TMOSFETs provide a reduced cell pitch compared with TMOSFETs with square and stripe patterns. Although TMOSFETs with a grid pattern reduce the channel area by approximately 10%, the cell density is increased by approximately 35%. Consequently, the specific on-resistance of the grid pattern is less than that of the square and stripe patterns. The forward blocking characteristics of the grid pattern are increased by the reduced impact ionization rate at the P/N junction. As a result, the figure-of-merit (FOM) of the grid pattern is increased by approximately 33%.
1. Introduction
Compared with silicon, the high critical electric field of silicon carbide (SiC) allows a low on-resistance to fabricate a thin epitaxial layer with a high doping concentration for a specified breakdown voltage. SiC MOSFETs with low on-resistance are useful in high-power and high-switching-speed applications such as DC-to-DC converters, motor drives, and electric vehicles. Researchers have attempted to minimize specific on-resistance (Ron,sp). With regard to device structure, trench-gate MOSFETs (TMOSFETs) have great potential for low on-resistance due to the absence of a JFET region and a small cell-pitch compared with planar gate MOSFETs [1,2,3,4]. Advanced process technologies including post-oxidation annealing in nitric oxide (NO) [5,6,7,8], self-aligned ohmic contact with two-step rapid thermal annealing (RTA) [8,9,10,11], and ion implantation at high temperatures [12,13] provide high-quality SiO2/4H-SiC interfaces with low contact resistance. A prevalent channel self-alignment method increases current density [14,15,16]. However, in existing photolithography areas, critical limitations of smaller cell pitches result from critical dimension control [17,18]. The pattern mask for the P+ source diode uses square and stripe patterns. The square pattern formed by etching all edge directions must be enlarged more than the stripe pattern to prevent a distorted pattern [19]. As the specific on-resistance is proportional to the cell pitch, a P+ source with a square pattern produces a high on-resistance.
In this study, a novel device architecture with a grid pattern is proposed to minimize the cell pitch. Unlike a conventional P+ source with stripe and square patterns, the proposed P+ source pattern architecture was fabricated beside the trench gate. Although the reduced channel area increases on-resistance, the proposed device provides a small cell pitch. Thus, the P+ source grid TMOSFETs provide lower on-resistance than both prevalent devices. In addition, this structure can increase the breakdown voltage about 11% more than the conventional structures due to a reduced 3-D effect at the P+/N+ junction and enhance the third-quadrant characteristics by increasing the P+ source areas.
2. Device Modeling and Simulation Methodology
Figure 1a–c show the 3-D structures of 1.7-kV conventional SiC TMOSFETs with a P+ source with square and stripe patterns and the proposed TMOSFETs with a P+ source with a grid pattern, respectively. The top view of TMOSFETs with a square-pattern P+ source is shown in Figure 1d. The square-type P+ source is placed intermittently around the N+ source. The square pattern size was set to 2 μm × 2 μm to consider alignment tolerance; thus, the half-cell pitch width was set to 2.3 μm. Figure 1e shows the top view of TMOSFETs with a stripe pattern P+ source and a half-cell pitch width of 2.0 μm. The stripe pattern is easily formed for two-direction patterning, allowing a smaller cell pitch than with a square pattern. The half-cell pitch width of TMOSFETs with a grid-pattern P+ source was set to 1.5 μm, with a trench width (WTRN) of 1.0 μm, N+ source width (WNP) of 1.0 μm, and P+ source width (WPP) of 1.0 μm, as shown in Figure 1f. A P+ source with a grid pattern was placed next to the trench gate. Although the channel width was reduced, this pattern enabled a reduced cell-pitch. To analyze the effect of the grid pattern on electrical characteristics, a P+ source length (LPP) was divided into five cases from 0.5 μm to 2.5 μm in the half-cell pitch in the y-direction.
For TMOSFETs with a 1.7-kV voltage rating, an N-type doping concentration of 6 × 1015 cm−3 with a drift thickness of 15 μm was designed using Sentaurus TCAD process tools. The detailed structural parameters presented in Table 1. TMOSFETs structural parameters were considered by experimental reference data [20,21]. Grid-pattern TMOSFETs of the P-well, N+ source, P+ source, and trench gate were designed using the fabrication sequence shown in Figure 2. The fabrication processes of the proposed TMOSFETs with P+ source grid pattern is the same as those of the conventional TMOSFETs with P+ source square and stripe patterns except photo-patterning of P+ source. The electrical characteristics of TMOSFETs with P+ source patterns were compared using the Sentaurus device. All simulations of electrical characteristics used the Lombardi model for carrier–carrier scattering by acoustic surface phonons and surface roughness. Shockley–Read–Hall (SRH) and an Auger were used in the generation-recombination process [22]. For the breakdown simulation, the van Overstraeten model was used for the avalanche generation model [22,23]. The breakdown voltage was determined when the current reached 1 μA.
3. Results and Discussion
The output characteristics of conventional TMOSFETs with square and stripe patterns are compared with those with a grid P+ source at Vgs = 9 and 20 V and Vds = 10 V in Figure 3. A grid pattern with a half-cell pitch of 1.5 μm provides a larger current than a square pattern with a half-cell pitch of 2.3 μm and a stripe pattern with a half-cell pitch of 2.0 μm. The difference in Ron,sp originates from the cell pitch. Thus, the Ron,sp of a grid pattern with a P+ source length (LPP) of 0.5 μm is less than the Ron,sp with a square pattern or stripe pattern, approximately 4.5% and 2.4% less, respectively.
Figure 4a shows the output characteristics of grid P+ source TMOSFETs with different LPP at Vgs = 9 and 20 V and Vds = 10 V. Maintaining a cell-pitch of 3.0 μm including the trench width, the N+ source width, P+ source width, and Lpp values of 0.5 to 2.5 μm with 0.5 μm steps, respectively, were used to examine the impact of Lpp on the specific on-resistance (Ron,sp). As LPP increased, the reduction in channel area produced an increase in Ron,sp. Figure 4b shows the measured Ron,sp with different half-cell pitches for the grid pattern and different P+ source lengths. As expected, a smaller cell pitch resulted in a lower Ron,sp. With a cell pitch of 3.0 μm, TMOSFETs with a grid pattern produce a lower Ron,sp than a square pattern for all Lpp values. A grid pattern with Lpp = 2.5 μm reduced the channel area approximately 50%; with a cell pitch of 3.0 μm, the channel area was reduced approximately 35%. Although the percentage decrease in the channel area was larger than the percentage decrease in cell pitch, Ron,sp for the grid pattern was less than that for the square pattern because the effect of the cell pitch was dominant. Compared with a stripe pattern, TMOSFETs with a grid pattern have a lower Ron,sp except with an Lpp of 2.5 μm. Thus, cell pitch is critical for determining the specific on-resistance. The grid pattern TMOSFEFs with the cell-pitch of 4.0 μm and 4.6 μm were fabricated to investigate the influence of the reduced channel areas. Maintaining the cell-pitch of 4.0 μm or 4.6 μm, the Ron,sp of grid pattern TMOSFETs compared to the Ron,sp of stripe pattern TMOSFETs or the Ron,sp of square pattern TMOSFETs, respectively. As a results, the stripe pattern or the square pattern have a lower Ron,sp than the grid pattern in the same cell-pitch because of the effect of the reduced channel areas in Figure 4b.
Figure 5a shows the forward blocking behaviors of all simulated TMOSFETs with stripe, square, and grid patterns with different cell pitches and LPP = 0.5 μm. The grid and stripe patterns produced a higher forward blocking voltage than the square pattern. In the TMOSFETs with a square pattern, a high impact ionization rate was observed at the P+/N+ junction at all edges of the square, and each point in the square pattern produced an increase in the electric-field stress, leading to a reduced breakdown voltage. To examine the impact of LPP on forward blocking characteristics, LPP of 0.5 μm, 1.0 μm, 1.5 μm, 2.0 μm, and 2.5 μm were designed to maintain the cell pitch. The role of the P+ source is to restrain a punch-through across the junction formed between the P-well and the N-drift region in forward blocking conditions [4]. This is not critical in deciding the blocking voltage in avalanche breakdown conditions; thus, high breakdown voltages remained regardless of the LPP, as shown in Figure 5b.
The equivalent circuit for the TMOSFETs with an integral p-body diode is shown in Figure 6a. To examine the impact of P+ source areas on the third-quadrant characteristics, the grid P+ source TMOSFETs with different LPP are compared in Figure 6b. As expected, an increase in LPP produces an increase in current density through the body diode in the third quadrant. Figure 6c shows the third-quadrant behaviors of TMOSFETs with square, stripe, and grid patterns and Lpp of 0.5 μm, 1.5 μm, and 2.5 μm. A shorter LPP (0.5 μm) in the grid TMOSFETs produces smaller quadrant behaviors than with conventional square and stripe TMOSFETs due to the small P+ source areas. However, a longer LPP (1.5 μm) in the grid TMOSFETs produces a larger current density than in the square p-body TMOSFETs due to the larger p-body area. In addition, all Lpp values produce smaller quadrant current than with the stripe p-body TMOSFETs.
The static characteristics of TMOSFETs with square, stripe, and grid patterns and all simulated results for Ron,sp, forward blocking behavior (BV), and figure-of-merit (FOM, BV2/Ron,sp) are compared in Table 2. Cell pitch (CP) is the most critical factor affecting Ron,sp. The smaller cell pitch of the TMOSFETs with a grid pattern produces a lower Ron,sp. For the same cell pitch, the channel area has a greater influence on Ron,sp. The P+ source for the stripe and grid patterns is influenced by greater forward blocking characteristics than the P+ source for the square pattern.
4. Conclusions
In this paper, 1.7-kV 4H-SiC trench-gate MOSFETs with a P+ source pattern are investigated in terms of P+ source dimension (length and width) on static characteristics, such as output characteristic and forward blocking voltage by 3-D numerical device simulation. It is demonstrated that P+ source pattern is the important factor in TMOSFETs due to cell-pitch and P+/N+ junction curve effect. The proposed TMOSFETs with P+ source with grid pattern reduced the cell-pitch approximately 35% and decreased the p-n junction effect. As a result, the grid P+ source TMOSFETs has a low specific on-resistance of 2.73 mOhm-cm2 and a high breakdown voltage of 2061 V. Compared with the conventional P+ source pattern TMOSFET structures, simulation results show that the Figure-Of-Merit (FOM, BV2/Ron,sp) of the proposed grid pattern TMOSFET is improved by approximately 33%.
Author Contributions
Conceptualization, J.-H.J., O.S. and H.-J.L.; data curation, J.-H.J. and M.-S.J.; formal analysis, J.-H.J., O.S. and H.-J.L.; investigation, J.-H.J. and M.-S.J.; project administration, H.-J.L.; writing—original draft preparation, J.-H.J.; writing—review and editing, J.-H.J., O.S. and H.-J.L. All authors have read and agreed to the published version of the manuscript.
Funding
This study was supported by a Korea Institute for Advancement of Technology (KIAT) grant funded by the Korean Government (MOTIE) (P0012451, The Competency Development Program for Industry Specialists). And the EDA tool was supported by the IC Design Education Center (IDEC), Republic of Korea.
Institutional Review Board Statement
Not applicable.
Informed Consent Statement
Not applicable.
Data Availability Statement
All data are presented in this paper in the form of figures.
Conflicts of Interest
The authors declare no conflict of interest.
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Figure 1.
(a) Conventional trench-gate MOSFETs with P+ source with square pattern, (b) stripe pattern, and (c) grid pattern. Top view of TMOSFETs with P+ source with (d) square pattern, (e) stripe pattern, and (f) grid pattern.
Figure 1.
(a) Conventional trench-gate MOSFETs with P+ source with square pattern, (b) stripe pattern, and (c) grid pattern. Top view of TMOSFETs with P+ source with (d) square pattern, (e) stripe pattern, and (f) grid pattern.
Figure 2.
Outline of grid P+ source TMOSFET fabrication sequence: (a) implant N+ source; (b) implant P+ source; (c) etch trenches; (d) gate oxidation; (e) deposit polysilicon gates.
Figure 2.
Outline of grid P+ source TMOSFET fabrication sequence: (a) implant N+ source; (b) implant P+ source; (c) etch trenches; (d) gate oxidation; (e) deposit polysilicon gates.
Figure 3.
Output characteristics of TMOSFETs with square, stripe, and grid pattern.
Figure 4.
(a) Output characteristics of grid pattern with Lpp of 0.5 to 2.5 μm with 0.5 μm steps; (b) specific on-resistance with square, stripe, and grid patterns with cell pitches of 3.0 μm, 4.0 μm, and 4.6 μm.
Figure 4.
(a) Output characteristics of grid pattern with Lpp of 0.5 to 2.5 μm with 0.5 μm steps; (b) specific on-resistance with square, stripe, and grid patterns with cell pitches of 3.0 μm, 4.0 μm, and 4.6 μm.
Figure 5.
(a) Forward blocking behaviors of square, stripe, and grid patterns with cell pitches of 3.0 μm, 4.0 μm, and 4.6 μm; (b) breakdown voltage of grid pattern with cell pitches of 3.0 μm, 4.0 μm, and 4.6 μm, and Lpp of 0.5~2.5 μm.
Figure 5.
(a) Forward blocking behaviors of square, stripe, and grid patterns with cell pitches of 3.0 μm, 4.0 μm, and 4.6 μm; (b) breakdown voltage of grid pattern with cell pitches of 3.0 μm, 4.0 μm, and 4.6 μm, and Lpp of 0.5~2.5 μm.
Figure 6.
(a) Equivalent circuit for MOSFETs with body diode; (b) third-quadrant behaviors for grid pattern with Lpp of 0.5~2.5 μm; (c) third-quadrant behaviors of square, stripe, and grid pattern with Lpp of 0.5 μm, 1.5 μm, and 2.5 μm.
Figure 6.
(a) Equivalent circuit for MOSFETs with body diode; (b) third-quadrant behaviors for grid pattern with Lpp of 0.5~2.5 μm; (c) third-quadrant behaviors of square, stripe, and grid pattern with Lpp of 0.5 μm, 1.5 μm, and 2.5 μm.
Table 1.
Device structural parameters.
| Parameter | Value | Unit |
|---|---|---|
| Thickness of drift layer | 15 | μm |
| Doping concentration of drift layer | 6 × 1015 | cm−3 |
| Trench depth and width | 2, 1 | μm |
| Doping concentration of P base | 2 × 1017 | cm−3 |
| Channel length | 0.7 | μm |
| Gate oxide thickness | 50 | nm |
| Width of inter layer dielectric (ILD) | 0.5 | μm |
| Half-width of cell pitch (y-axis) | 5 | μm |
| Half P+ source size (square pattern) | 1 × 2 | μm |
| Half P+ source size (stripe pattern) | 0.5 × 5 | μm |
| Half-width of cell pitch (square pattern) | 2.3 | μm |
| Half-width of cell pitch (stripe pattern) | 2.0 | μm |
| Half-width of cell pitch (grid pattern) | 1.5 | μm |
| Half-width of P+ source (grid pattern) | 1.5 | μm |
| Half-length of P+ source (grid pattern) | 0.5–2.5 (+0.5) | μm |
Table 2.
Summary of device structures and static characteristics.
| Device Structure | Simulation Results | ||
|---|---|---|---|
| Specific On-Resistance (Ron,sp) [mOhm-cm2] | Forward Blocking (BV) [V] | Figure-of-Merit (FOM) [MW/cm2] | |
| Square pattern (CP = 4.6 μm) | 2.86 | 1830 | 1172 |
| Stripe pattern (CP = 4.0 μm) | 2.80 | 1998 | 1426 |
| Grid pattern (CP = 3.0 μm, Lpp = 0.5 μm) | 2.73 | 2061 | 1556 |
| Grid pattern (CP = 3.0 μm, Lpp = 1.0 μm) | 2.74 | 2061 | 1549 |
| Grid pattern (CP = 3.0 μm, Lpp = 1.5 μm) | 2.76 | 2061 | 1539 |
| Grid pattern (CP = 3.0 μm, Lpp = 2.0 μm) | 2.78 | 2061 | 1526 |
| Grid pattern (CP = 3.0 μm, Lpp = 2.5 μm) | 2.82 | 2061 | 1508 |
| Grid pattern (CP = 4.0 μm, Lpp = 0.5 μm) | 2.81 | 2002 | 1426 |
| Grid pattern (CP = 4.0 μm, Lpp = 1.0 μm) | 2.83 | 2003 | 1420 |
| Grid pattern (CP = 4.0 μm, Lpp = 1.5 μm) | 2.85 | 2001 | 1406 |
| Grid pattern (CP = 4.0 μm, Lpp = 2.0 μm) | 2.88 | 2002 | 1393 |
| Grid pattern (CP = 4.0 μm, Lpp = 2.5 μm) | 2.92 | 2000 | 1370 |
| Grid pattern (CP = 4.6 μm, Lpp = 0.5 μm) | 2.88 | 1903 | 1260 |
| Grid pattern (CP = 4.6 μm, Lpp = 1.0 μm) | 2.89 | 1974 | 1347 |
| Grid pattern (CP = 4.6 μm, Lpp = 1.5 μm) | 2.92 | 1962 | 1320 |
| Grid pattern (CP = 4.6 μm, Lpp = 2.0 μm) | 2.95 | 1939 | 1274 |
| Grid pattern (CP = 4.6 μm, Lpp = 2.5 μm) | 3.00 | 1927 | 1238 |
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MDPI and ACS Style
Jeong, J.-H.; Jang, M.-S.; Seok, O.; Lee, H.-J. Effect of P+ Source Pattern in 4H-SiC Trench-Gate MOSFETs on Low Specific On-Resistance. Appl. Sci. 2023, 13, 107. https://doi.org/10.3390/app13010107
AMA Style
Jeong J-H, Jang M-S, Seok O, Lee H-J. Effect of P+ Source Pattern in 4H-SiC Trench-Gate MOSFETs on Low Specific On-Resistance. Applied Sciences. 2023; 13(1):107. https://doi.org/10.3390/app13010107
Chicago/Turabian StyleJeong, Jee-Hun, Min-Seok Jang, Ogyun Seok, and Ho-Jun Lee. 2023. "Effect of P+ Source Pattern in 4H-SiC Trench-Gate MOSFETs on Low Specific On-Resistance" Applied Sciences 13, no. 1: 107. https://doi.org/10.3390/app13010107
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