A Two-Dimension Time-Domain Comparator for Low Power SAR ADCs

: This paper presents a two-dimension time-domain comparator suitable for low power successive-approximation register (SAR) analog-to-digital converters (ADCs). The proposed two-dimension time-domain comparator consists of a ring oscillator collapse-based comparator and a counter. The propagation delay of a voltage controlled ring oscillator depends on the input. Thus, the comparator can automatically change the comparison time according to its input difference, which can adjust the power consumption of the comparator dynamically without any control logic. And a counter is utilized to count the cycle needed to finish a comparison when the input difference is small. Thus, the proposed comparator can not only provide the polarity of the input, but also the amount information of the input, which helps to skip most of the SAR cycles when the initial input is small. Thus, most energy can be saved when the initial input is small. The proposed time-domain comparator is designed in 0.18 μm CMOS technology. Simulation results demonstrate that the comparator can not only save power consumption, but also give the design flexibility, and the current is only nA level when the supply voltage is 0.6 V.


Introduction
With the development of Internet of Things (IoTs), there are growing demands for powerlimited applications, such as wireless sensor networks, RFID systems, wearable devices, biometrics [Verma and Chandrakasan (2007) ;Su, Sheng, Xie et al. (2019); Chang, Wang and Wang (2007) ;; Lee, Park, Park et al. (2011); Zhu and Liang (2015); Su, Sheng, Leung et al. (2019) ;Elzakker, Tuijl, Geraedts et al. (2010); Wang, Gu, Liu et al. (2019)]. The analog-to-digital converter (ADC), as a critical block for sensor interface, should meet the stringent power budget in these power limited systems. The successive approximation register (SAR) ADC is the most preferred candidate for those energy-limited applications because of its medium resolution, medium speed, low power, low design complexity and friendly technology scaling [Liu, Sheng and Zhu (2016); Chang and Hsieh (2018) ;Chung, Yen, Tsai et al. (2018); Fu and Pun (2018)]. SAR ADC mainly consists of three blocks: comparator, digital-to-analog converter (DAC) and SAR control logic. In most SAR ADC designs, the comparator is in voltage domain  ;Liu, Chang, Huang et al. (2010); Wang, Liu, Sheng et al. (2018); Zhu, Qiu, Liu et al. (2015); Ahmadi and Namgoong (2015); Yu, Gao, Liu et al. (2019)]. The power consumption of these voltage domain comparators is determined by the resolution of ADC, and it cannot be adjusted dynamically according to the input difference, which wastes lots of energy when the input signal difference becomes larger. In order to reduce the power consumption, comparator energy scaling techniques have been developed [Lee, Park, Park et al. (2011);Tai, Hu, Chen et al. (2014); Liu (2016)]. Two comparator architecture in Tai et al. [Tai, Hu, Chen et al. (2014); Liu (2016)] uses one comparator for coarse comparisons, and the other for fine comparisons. And time-domain comparators have also been proposed to reduce the power consumption [Lee, Park, Park et al. (2011);Shim, Jeong, Myers et al. (2017)]. However, these techniques complex the design of SAR ADC by extra control logic, which increases the design complexity. The ring oscillator collapse-based comparator in time-domain can achieve automatic energy scaling according to the input difference [Shim, Jeong, Myers et al. (2017)], but the delay cells in the comparator stacked four MOS transistors, which increases the power supply voltage. This paper proposes a two-dimension time-domain comparator, which can achieve automatic energy scaling according to the input difference. Furthermore, a counter is utilized to detect the edge cycles needed to finish a comparison cycle, which makes the comparator provide additional information. Thus, the comparator can not only provide the polarity of the input, but also the amount of the input difference, which helps to skip most of the SAR cycles when the initial input is small. The rest of the paper is organized as follows. Section 2 presents the structure and operation principle of the proposed comparator. Section 3 analyzes the performance of the comparator. Simulation results are given in Section 4. And Section 5 concludes this paper. Fig. 1 shows the structure of the two-dimension time-domain comparator, which consists of inverter delay cells, two NAND gates and a counter. Each delay cell has two inverters, and each inverter has one input voltage: one is PMOS input and the other is NMOS input. Compared with the comparator in Shim et al. [Shim, Jeong, Myers, et al. (2017)], the proposed delay cell can achieve a lower supply voltage, which helps to reduce the power consumption. The operation principle is illustrated in Fig. 2. As the counter does not influence the oscillation of the inverter loop, the counter is omitted in Fig. 2 for simplification. As shown in Fig. 2(a), when the start signal ST is low, the comparator is in a reset state, the output OUT is logic high, and the number of CNT is zero. The oscillation loop is in a disabled state. When ST goes from low to high, the comparator starts to work. As Fig. 2(b) shows, NAND gates A and B will produce a rising edge, the outputs of the NAND gates will be a falling edge, and these two falling edges will propagate through delay cells. Supposing Vip>Vin, the edge originating from NAND gate A travels faster than the edge of NAND gate B. When the edge of gate A catches up with the edge of gate B, the oscillation of the inverter loop will stop, and the comparison is finished. As Vip is larger than Vin, OUT is high when the comparison is finished. Otherwise, OUT is low. When Vip is larger than Vin, the comparison result OUT is a high level, and the oscillation cycle depends on the input difference. If Vip is larger than Vin with a large amount, the edge coming from NAND B propagates much faster than that of NAND A, and the comparison will finish in a short time as shown in Fig. 3(a). When Vip is only a little larger than Vin, then the edge coming from NAND B travels at a speed very close to that of NAND A, and it will take a long time to finish the comparison as Fig. 3(b) illustrates. In this case, the cycles needed are larger than those in Fig. 3(a), and the number CNT of the counter is larger than that of Fig. 3(a). When Vip is smaller than Vin, OUT will be low. Thus, the comparison time depends on the input difference, which can be regarded as the energy consumption during a comparison cycle that can automatically adjust according to the input difference. The number CNT of the counter can indicate the amount of the input difference, which gives additional information of the comparator. As shown in Fig. 2, the inverter loop consists of the inverter cell with alternated NMOSgated and PMOS-gated current starved delay cells. For simplicity, the inverter loop can be modeled as a chain of multiple identical units NMOS-gated current starved delay cell. Fig. 4 shows the model of the unit delay cell with defined parameters. Assuming the load of each inverter cell is much larger than parasitic capacitors of MOS transistors, the delay of NAND gates in Fig. 2 and noise of MOS transistors with a red line in Fig. 4 can be neglected. Then the unit delay cell can be modeled as a switch with a threshold of VDD/2. When the input of the inverter goes from low to high, the output Vout starts to discharge through the current source controlled by one of the differential inputs. Assuming the input difference voltage is in V ∆ , the time needed to discharge Vout to VDD/2 can be expressed as

Structure and operation principle of the proposed comparator
where I0 denotes the current when in V ∆ equals to 0, CL is the load capacitance. The time delay between the two edges originating from NAND gates A and B can be written as where gm is the small-signal transconductance of the transistor when the bias voltage is around VDD/2. Then the gain of voltage to time conversion of N stages is And the propagation delay of each edge can be expressed as (Vip>Vin) where tA and tB are the propagation delay of each unit delay cell. As shown in Fig. 2, the working principle can be regarded as two edges coming from NAND gates A and B chase each other. When the edge with faster propagating speed catches up with the lower one, the comparison is finished. Thus, the time of a comparison cycle can be considered as a chase problem. Assuming there are N unit delay cells in the inverter loop, the initial distance of these two edges is N/2 (neglecting the delay of two NAND gates), and the comparison time tcomp approximately satisfies And the cycles the counter detected can be expressed as The amount of the input difference is reflected by CNT. Thus, the comparator can not only provide the polarity information of the inputs but also the amount of the input difference. The average current of the unit delay cell drawn from VDD is I0, the power consumption for a comparison cycle is

Noise analysis
The noise of the comparator can be analyzed using the noise model shown in Fig where ro is the output resistance, and γ the noise factor, k is the Boltzmann constant, T is the absolute temperature. The delay fluctuation d t ∆ due to the noise can be expressed as Since the comparator output accumulates the noise effect of every delay stage, which are statistically independent, the standard deviation of time error of the whole comparator where Vos is the offset voltage. As each unit cell is independent, the deviation of the offset due to N-stage is Thus, the input offset voltage Vos_N can be derived by Eq. (14) and Eq. (15):

Simulation results
The proposed comparator is designed in 0.18 μm TSMC CMOS technology, and simulations are carried out by Cadence Spectre. The aspect ratio of all PMOS transistors is set to 4 μm/5 μm and that of all NMOS transistors is set to 1 μm/5 μm. The current against input under different VDD is shown in Fig. 7 when 20 delay cells are included in the inverter loop. The power consumption can be adjusted automatically according to the input voltage difference. During simulations, the input difference is from 1 μV to the corresponding full-scale voltage. The current consumption decreases as the input difference increases when the input difference is small, and the current consumption is well satisfied with the analysis in Section 3 as the model used in the analysis is a smallsignal model. When the input difference becomes larger, the circuit should be considered as a large signal mode, and the current consumption increases sharply with the input voltage as can been seen from Fig. 7. The knee points are about tens of mV. The comparison time against the input voltage is illustrated in Fig. 8. The comparison time decreases when the input voltage becomes larger. This is because when the input voltage difference becomes large, the edge generated from one of the NAND gates propagates much faster than the other one, then the oscillation will collapse more quickly. Tab. 1 shows the number CNT of the counter against the input voltage under different VDD when the delay cell stages are 20. When the input voltage is larger than 0.1 mV, the CNT is always 1. And the CNT will change with a certain amount of the input voltage difference. The lower the supply voltage is, the more the CNT changes with the input voltage. The impact of delay cells on CNT is also evaluated and simulation results are shown in Tab. 2. It can be seen that the stages of delay cell have an impact on CNT, when more delay cell stages are incorporated, CNT is larger under the same input voltage. Thus, the sensitivity of CNT can be adjusted by the supply voltage and the stages of the delay cell. This characteristic of the comparator enables the ability of detecting week signals.

Conclusion
A time-domain comparator is presented in this paper. The comparator consists of a ringoscillator collapse-based comparator and a counter, which can provide not only the polarity of the input but also the amount of the input difference. And the power consumption of the comparator can be adjusted automatically according to the input, which saves the power consumption when applied to SAR ADC. Designed in 0.18 μm CMOS technology, the current consumption of a comparison cycle is at the nA level when the supply voltage is 0.6 V.