A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits

Yoji BANDO; Satoshi TAKAYA; Toru OHKAWA; Toshiharu TAKARAMOTO; Toshio YAMADA; Masaaki SOUDA; Shigetaka KUMASHIRO; Tohru MOGAMI; Makoto NAGATA

doi:10.1587/transele.E94.C.495

Special Section on Circuits and Design Techniques for Advanced Large Scale Integration

A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits

Yoji BANDO, Satoshi TAKAYA, Toru OHKAWA, Toshiharu TAKARAMOTO, Toshio YAMADA, Masaaki SOUDA, Shigetaka KUMASHIRO, Tohru MOGAMI, Makoto NAGATA

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Keywords: on-chip monitor, power supply noise

JOURNAL RESTRICTED ACCESS

2011 Volume E94.C Issue 4 Pages 495-503

DOI https://doi.org/10.1587/transele.E94.C.495

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Abstract

A continuous-time waveform monitoring technique for quality on-chip power noise measurements features matched probing performance among a variety of voltage domains of interest in a VLSI circuit, covering digital Vdd, analog Vdd, as well as at Vss, and multiple probing capability at various locations on power planes. A calibration flow eliminates the offset as well as gain errors among probing channels. The consistency of waveforms acquired by the proposed continuous-time monitoring and sampled-time precise digitization techniques is ensured. A 90-nm CMOS on-chip monitor prototype demonstrates dynamic power supply noise measurements with ±200mV at 2.5V, 1.0V, and 0.0V, respectively, with less than 4mV deviation among 240 probing channels.

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