Abstract
Data-intensive applications have a huge demand on processor-memory communication. To reduce the amount of data transfers and their associated latency and energy, Compute-in-Memory (CIM) architectures can be used to perform operations ranging from simple binary operations to more complex operations such as additions and matrix-vector multiplications directly within the memory. However, proper adjustments to the memory hierarchy are needed to enable the execution of CIM operations. To evaluate the trade-off between the usage of different emerging non-volatile memories for CIM and conventional computing architectures, this work extends the widely used gem5 simulation framework with an extensible timing-aware main memory CIM simulation capability. This framework is used to analyze the performance of CIM extended main memory with various emerging memory technologies, namely Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM), Redox-based RAM (ReRAM) and Phase-Change Memory (PCM). We evaluate different workloads from the PolyBench/C benchmark suite and other selected examples. In comparison to a processor-centric system, the results show a significant reduction in execution time for the majority of applications.
About the authors
M. Sc. Vincent Rietz received his B. Sc. degree in electrical engineering and his M. Sc. degree in computer science from the Karlsruhe Institute of Technology (KIT), Germany in 2018 and 2022, respectively. During his studies he specialized on reliability, implementation and test of embedded systems. In his master’s thesis he focused on architectural simulation of compute-in-memory using emerging storage technologies. Currently, he is working as an embedded software engineer in Karlsruhe.
Dr. Christopher Münch received his Bachelor’s, Master’s, and Ph.D in Computer Science from the Karlsruhe Institute of Technology in 2014, 2017, and 2023, respectively. His special interest are neuromorphic computing and emerging memory technologies.
M. Sc. Mahta Mayahinia received her B.s in Electrical and Electronic Engineering from Shahid Beheshti University, Tehran, Iran, and her M.s in Computer System Architecture from Sharif University of Technology, Tehran, Iran in 2015 and 2018 respectively. In 2020 she joined the CDNC group of Professor Tahoori at KIT University, Karlsruhe, Germany. Her current research interest is VLSI design, Computer Architecture, and Computation in memory.
Prof. Dr. Mehdi B. Tahoori (M’03, SM’08, F’21) received the B.S. degree in computer engineering from the Sharif University of Technology, Tehran, Iran, in 2000, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, in 2002 and 2003, respectively. He is currently a Full Professor at the Karlsruhe Institute of Technology, Karlsruhe, Germany. In 2003, he was an Assistant Professor with the Department of Electrical and Computer Engineering, Northeastern University, where he became an Associate Professor in 2009. From August to December 2015, he was a visiting professor at VLSI Design and Education Center (VDEC), University of Tokyo, Japan. From 2002 to 2003, he was a Research Scientist with Fujitsu Laboratories of America, Sunnyvale, CA. Prof. Tahoori was a recipient of the National Science Foundation Early Faculty Development (CAREER) Award. He has received a number of best paper awards at various conferences and journals including ICCAD, FPL, TODAES, and TVLSI. He is a fellow of the IEEE and a recipient of European Research Council (ERC) Advanced Grant.
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Author contributions: All the authors have accepted responsibility for the entire content of this submitted manuscript and approved submission.
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Research funding: None declared.
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Conflict of interest statement: The authors declare no conflicts of interest regarding this article.
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