Fault-Tolerance in Field Programmable Gate Array with Dynamic Voltage and Frequency Scaling

The purpose of this paper is to present a methodology for Field Programmable Gate Array based designs, either to reduce power consumption or to boost performance during product lifetime. The methodology includes a performance sensor, focusing long-term parametric variations like Process, power-supply Voltage, Temperature and Aging, and a Single Event Upsets' sensor, focusing intermittent variations like radiation effects and disturbances. The performance sensor predictively detects errors in critical paths, either allowing power-supply voltage to be reduced, or clock frequency to be raised, creating a dynamic voltage and frequency scaling technique to reduce power or to increase circuit performance. Fault-tolerance is enhanced not only by predictively detecting errors in performance sensors, but also by using of traditional fault-tolerance solutions like Triple-Modular Redundancy or Error Correcting Codes. The Single Event Upsets' sensor monitors Single Event Upsets in Block Random Access Memory, which allows a faster evaluation of radiation effects than the configuration memory monitoring, thus increasing error detection and correction. The Hardware Description Language sensor's functionality is defined by the designer, according to the target circuit configuration in the Field Programmable Gate Arrays' structure. The adaptive scheme uses an Automatic Voltage and Frequency Controller to modify power-supply voltage and/or clock frequency, while still guaranteeing safe operation. The built-in performance sensors monitor performance deviations in pre identified critical paths during circuit operation. The clock frequency increase is made possible by reducing the pessimistic safety margins defined by standard simulation tools to account for variability. The performance sensors delay margins are programmable, so the most adequate delay margin can be used to guarantee safe operation. Conversely, the same performance can be achieved with lower power-supply voltage. Simulation and experimental results with Virtex 5 and Spartan 6 boards show that significant performance improvements (typically, 30%) can be achieved with this methodology.