Robust Low Power Embedded SRAM: From System Considerations to Cell Design

SRAM will remain important for digital ICs because of its low latency, although it faces strong competition from external DRAM. With the recent attention for “green” products, power reduction in digital systems stays in focus and therefore so does low power SRAM design. For many systems, properly designed SRAM has a low contribution to total SoC power, which means that the significant design effort required for low voltage SRAM does not pay off. Several techniques are available to achieve both low active and standby power SRAM without using a low supply voltage. When even after power optimization the SRAMs consume a large part of system power, low voltage SRAM further reduces power consumption. Using statistical simulation techniques, robustness for low power SRAM is ensured without over-design.