Power Management Through Dynamic Frequency Scaling for Low and Medium Bit-Rate Digital Receivers
Low and medium bit-rate receivers are met in a wide range of applications including the popular GSM and DECT telecommunication terminals. In principle, receivers falling in this class employ oversampling for synchronization purposes. This paper introduces a novel power-aware architecture for low and medium bit-rate digital receivers that implements power management by dynamically scaling the operation frequency. A real-life DECT receiver is used to compare the conventional and the proposed architecture. Experimental results indicate that the proposed architecture presents significantly reduced power consumption for a negligible increase in area and performance decrease. Specifically, depending on the selected oversampling ratio and the receiver structure, a 40% up to 70% power reduction has been obtained with a 2% and 1.2% increase in area and delay, respectively.
Keywords: COMMUNICATIONS; DIGITAL RECEIVERS; DYNAMIC POWER MANAGEMENT; LOW-POWER DESIGN; VLSI
Document Type: Research Article
Publication date: 01 December 2006
- The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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