A Single DC Source Generalized Switched Capacitors Multilevel Inverter with Minimal Component Count

. Tis paper presents a new single-source switched capacitor- (SC-) based multilevel inverter (MLI) design with a boosting potential of three times the supply voltage. To produce a waveform with seven output voltage levels, the suggested switching capacitor inverter consists of eight switches, single diode


Introduction
Te multilevel inverter is becoming more popular in industrial and academic applications because of its enhanced power quality, efciency, low losses, and total harmonic distortion (THD). Te use of MLIs provides signifcant benefts in the felds of medium-and high-voltage applications [1,2]. In comparison to conventional inverters, it has a better power handling capacity and a higher degree of modularity, and it requires a relatively smaller amount of fltering. Because of its fexible design, MLI can be used in many diferent felds of electrical engineering. Generally, there are three types of conventional MLIs such as fying capacitor (FC) MLI, diode-clamped (DC) MLI, and Cascaded H-bridge (CHB) MLI. Tey enclose some disadvantages in terms of voltage stress, the number of active-passive components, a capacitor's voltage maintaining its own selfbalancing voltage, and voltage gain.
For example, DC MLI and FC MLIs have difculties with capacitor voltage balancing and need multiple switching components for a multilevel voltage generation. Te cascaded H-bridge MLI is one such device that receives extensive use in renewable energy integration system (REIS). Te CHB MLI is one of the most popular topologies in the literature because of its simple and extensible design [3].
Numerous isolated sources (DC) are used in the MLI topologies proposed in [4][5][6]. As a result, it preserves to be used in either as asymmetrical or a symmetrical confguration. All of these MLI topologies feature a modular design, making it simple to add more basic cells or subcells to increase the output voltage. But each of these topologies requires a much higher amount of isolated DC sources at input and power components, which fallout in an increase in size. Tis, in turn, causes the circuit to be cumbersome and expensive. Te problem is caused by the fact that there are several DC sources available. However, these are excellent for locations that have access to a variety of input sources, such as renewable forms of energy. Te output voltages are generated by a novel MLI topology in which voltage sources are connected in a series-parallel confguration. H-bridge makes it simple to combine numerous DC sources into a renewable energy system [7,8].
Te switched capacitor SC topologies in recent years have a great interest in the research feld because of some excellent features such as (i) boosting the ability of the input voltage, (ii) multiple DC voltage sources can be replaced by capacitors, and (iii) inherent self-balancing property of capacitors. Tese factors reduced the weight, size, and costs. Te series-parallel combination of the DC source and capacitor of the multilevel inverter has good modular structure features and capacitor voltage balancing without any external balancing circuit presented in [9][10][11]. Multiple sources advocated in [12,13] have back-end H-bridge. Due to the fact that it comprises various sources, it becomes complicated and expensive. Te authors in references [13][14][15][16][17][18][19] further describe an active NPC capacitor inverter in the midst of a similar principle with a voltage-boosting capability of 1.5V DC . Te topology described in [20,21] has a modular SC structure with a minimum number of switching components. Another generalized structure of the SC technique reduces the total standing voltage for generating seven voltage levels, but switching components is increased [22][23][24][25][26]. Te topology proposed in [22] reduced the blocking voltage, i.e., the voltage stress is within the supply voltage but larger numbers of passive and active components are used. A cross-switched triple gain SC topology is presented in [27][28][29]. However, this topology sufers several drawbacks, such as it includes a larger number of switching components and higher discharging time compared to the charging time of capacitors. Te preceding paragraphs inspire the development of a novel generalized SC-based topology with less active and passive components, boosting capability, and self-balancing capability.
In light of these concerns, this study proposes a unique compact SC inverter with the following noteworthy characteristics: (a) Te capacitors are self-balancing. (b) Power supply voltage-boosting capabilities (i.e., three times the supply voltage). (c) Less than 50% of switches operate for any level of voltage. (d) Each fundamental cycle has an identical number of repetitions for both charging and discharging. (e) Te smallest possible number of switching components.
(f ) Te switching components are subjected to less voltage stress.
(g) Te generalized structure of SCMLI is easily achievable.
Te enduring sections of the article are structured as follows: Section 2 includes a description of the suggested topology, the operational principle of diferent states, the fnding of the most optimal capacitance values, the inherentbalancing capability of capacitors, and the modulation scheme. Loss analysis of the SCMLI topology is presented in Section 3. Section 4 discusses the generalized structure. Section 5 discusses the simulation process as well as the interpretation of experimental results. Te relative analysis is introduced in Section 6 to confrm the signifcance of the structural design. Discussion on fndings and applicability are also presented. Finally, Section 7 concludes with the highlights of the suggested topology. IGBTs not including antiparallel diode are considered. A threefold voltage-boosting capability is provided by the proposed topology (0, ±1V DC , ±2 V DC , ±3V DC ). Te capacitors, C 1 and C 2 , are inherently self-balanced. It has four pairs of complementary switches (i.e., S 1 S 2 .S 3 S 4 , S 5 S 6 , S 7 S 8 ) to evade the short circuit. Te charging path of the capacitors and load is indicated by dotted red and black lines. Table 1 explains the conceptual topology's valid switching states. Te "OFF" and "ON" states of the switches are represented by "0" and "1." Table 2 summarizes the stresses on the switches.  Table 1 and the analogous circuit design illustrated in Figure 2.   Figure 2(h) depicts the corresponding circuit diagram of this state.

Design of Optimum Values of the Capacitor.
Te capacitors get charged while they are connected in shunt fashion by way of an isolated DC voltage source (V DC ) and discharge their deposited energies to the output when connected with the supply source. Te discharging values of capacitance are expressed as where θ x and θ y are the longest releasing time span, I P is the maximum load current values, and ∅ is the power factor angle. Te values of θ x and θ y can be measured as follows [26] from Figure 3 Te optimal capacitance values are determined by the subsequent factors: (i) peak load current values, (ii) highest discharging period, and (iii) lowest voltage ripple (∆V) [17,18]. As a result, the best possible capacitance values can be mentioned as Te maximum voltage spikes may be computed for pure resistive load Te details of self-balancing based on the parallel/series procedure of the switched capacitors as shown in Figure 2 make the capacitors self-balanced automatically [22].

Modulation Strategy.
Te suggested inverter is switched using a technique called phase disposition pulse with modulation (PDPWM). In this technique, a 50 Hz sine wave (u) is compared with eight constant signals (0+, 1/3, 2/3, 1, 0−, −1/3, −2/3, and −1), and the results are fed into a "AND" gate and a "Ex-OR" gate to yield the desired outputs  States S1 S2 S3 S4 S5 S6 S7 S8 Output voltage (P 1 , P 2 , P 3 , P 11 , P 22 , and P 44 ) as shown in Figure 3(a). In the second step, the sine wave is compared with six 1/3-height carrier signals e 1 , e 2 , e 3 , e 4 , e 5 , and e 6 to produce the corresponding output signals j 1 , j 2 , j 3 , j 11 , j 22 , and j 33 , as shown in Figure 3(b) and graphically in Figure 3(c). Each of the signals P 1 , P 2 , P 3 , P 4 , P 11 , P 22 , P 33 , and P 44 , as well as their inverted counterparts, are fed into separate "AND" gates in the auxiliary circuit 2 of Figure 3(b), which in turn generate the corresponding outputs x 1 , y 1 , x 2 , y 2 x 3 , x 11 , y 11 x 22 , y 22 and y 3 . Driving pulses for switches S 1 − S 8 can be generated International Transactions on Electrical Energy Systems from the outputs of the auxiliary circuit 2 in Figure 3(b) using "OR" gates and the equations (8)- (14). International Transactions on Electrical Energy Systems

Power Loss Analysis
Tis suggested topology has three sorts of losses. Tese losses are (a) conduction losses, (b) switching losses, and (c) ripple losses.
3.1. Switching Losses (P sw ). While switches are bowed ON and OFF, switching losses occur. Te power losses in favour of every distinctive switch during ON and OFF are shown in Figure 4 [13]. Turn-ON power losses are Turn-OFF power losses are where V is the voltage across the switches before and after activation. I on and I off are the current fowing through the switches once they are turned on. t on and t off are the switch's OFF and ON times. Tus, the proposed topology's total losses associated with switching (P sw ) is stated in where n represents level count and m represents switch count.

Conduction Losses (P con ).
As a result of turning on the power switch, conduction losses are incurred. During the ON-state, the internal resistance of the power switch (R S ) and diode (R D ) wasted power. In general, conduction losses are now the sum of the all switches and diodes power losses.
where V s,on and V d.on are the ON-state voltage drop of the switch and diode, respectively. I d,rms , I s,rms , and I d,avg , I S,avg be the RMS and average current of the diode and switch, respectively.
So, the proposed SC-MLIs' overall power losses associated with conduction are given by where n and k represent switch count and conduction paths, respectively.

Ripple Losses (P R ).
Te capacitor charges when a parallel connection is made between it and the power source. Te capacitor's charging current creates ripple losses. So, the voltage ripple can be illustrated [25] from equations (5) and (7) as Terefore, the total power losses (P T ) are P T � P sw + P c + P R . Figure 1 shows a simple architecture that can easily be expanded to create a higher output voltage via simply adding SC cells or connecting them in series. By using a SC-based multilevel inverter, increasing the number of SC units increases the output voltage. Capacitors determine the maximum output voltage and serve as virtual sources. Te 9-level output voltage is made achievable by including an additional SC unit in the suggested design. Te generalised confguration of the proposed SCMLI topology for the expansion is depicted in Figures 5(a) and 5(b). Te generalised arrangement of MLI with a SC unit is shown in Figure 5(a), and the generalised structure with a cascade tie is shown in Figure 5(b). SCMLI's broad equation can be stated in terms of SCs. As a result, Table 3 lists the recommended SCMLI inverter switches, diode, and output level.

Comparative Assessment
Te suggested SCMLI topology is compared to the sevenlevel SC topologies provided in Table 4 to assess its benefts. Among other criteria, the proposed architecture was assessed in provisos of maximum blocking voltage (MBV), gain, switch count per level, TSV, and cost function. Te proposed and chosen topologies share Cost function is defned as Te weight factor α will be near to unity and it completely depends on switching components' signifcance or the maximum load voltage. In the proposed architecture, this factor (α) is "1", i.e., both switching components and TSV pu are equally important. As the name implies, TSV pu is the sum of all each switch voltage stresses divided by the maximum load voltage. Tese two factors (F C/L , CF) decide the cost, size, and weight of the inverter. Te proposed architecture is comprised of only 8 switches, one diode, and two capacitors in order to provide a 7-level output. It is noticed that the value of F C/L and CF of the anticipated topology is not as much as the recently proposed SCMLI topologies mentioned in Table 4 except the ones in [31,32,35]. However, the gain in [30][31][32][33][34][35] are less than the proposed one. Tis shows the said topology is associated with a smaller number of the driver unit, heat sinks, protection units, etc. Henceforth, the proposed converter's overall system cost, weight, and size are low among the state-of-the-art topologies. Tese features make the suggested topology more attractive and advanced. However, the topologies advocated in [16,18,22,[30][31][32][33][34] have a higher number of capacitor unit which means their stress and inrush current are very high, which degrades their reliability.

Simulation Results.
A MATLAB/Simulink model of a seven-level SC inverter is constructed to test the viability of the proposed MLI. Table 5 displays the simulation parameters used in the analyses. Te suggested inverter steady-state performance has been simulated under an R-L load (30 and 80 mH). Figure 6(a) depicts current and voltage waveforms.    International Transactions on Electrical Energy Systems Each step's voltage is 50 V, and the highest output is 150 V. Due to the input source of 50 V, an increase gain of 3 is realized, which agrees with the theoretical notion. Te fnding that the 2 capacitors are inherent-balancing with diminutive voltage ripples supports the investigation of balancing the capacitor voltage. Te consequences of the rapid shift in load are shown in Figure 6(b). Te fndings show the inverter's ability to work across an extensive choice of loads, with a peak voltage of 3V DC at a 7-level.
Te proposed inverter can respond to variations in carrier wave frequency accurately. Figure 6 shows the voltage and current output vs. frequency (c). In all instances, it was discovered that the inverter exhibits a quick transient reaction (200 Hz to 2 kHz).Te output voltage varies when the modulation index (M) amplitude varies, as seen in Figure 6(d). When M lowers from 0.9 to 0.75 and subsequently to 0.2, the output voltage steps down from seven levels to fve levels and then three levels, as shown in Figure 6(d). Te speedy completion of the transient operations conveys the high transient performance of the proposed inverter. To investigate power losses, the proposed model was simulated using PLECS-based software, and the IGBTs datasheet was imported. Te THD analysis of voltage and current is shown in Figures 6(e) and 6(f). Figure 6(g) depicts the power loss distribution for a purely resistive load. Overall, the proposed topology has an efciency of around 96.2%.

Experimental
Results. Experimentation with a research laboratory model is given here to authenticate the theoretical conclusions and reveal the viability of the suggested topology in both steady-state and dynamic circumstances.
Te suggested inverter steady-state operation has been tested using an R-L load model (30 and 80 mH). Figure 7 depicts a voltage and current waveform (a). Te maximum output is 150 V, with 50 V increments. With a 50 V input voltage, a boost gain of 3 is obtained, which is reliable through the theoretical expectation. Figure 7 depicts the experimental waveform of the step change load's load voltage v o , load current i o , and voltage across the capacitors (b). When there is a sudden shift in load, the load voltage level remains constant. Te waveform shows that when a step change in load is introduced, the voltage across the two capacitors is inherently balanced. Figure 7(c) also depicts experimental results for scenarios with a variable switching frequency (in this, i.e., 100 Hz and 5 kHz). It is vital to note that the output voltage level remains constant under these situations.
As seen in Figure 7(d), the output voltage varies as the modulation index amplitude changes. Furthermore, as seen in Figure 7(d), as M falls from 0.9 to 0.5, then to 0.2, the quantity of output voltage steps lowers from seven to fve, then to three. Te maximum efciency obtained from the experimental setup by the use of a power quality analyzer (Fluke 43B) is 97.16%. Finally, experimental results reveal that the proposed design performs adequately in both dynamic and steady-state circumstances.

Discussions on Findings and Applicability.
Te suggested design generates a seven-level waveform with three times the voltage gain, as shown by modelling and experimental results. It has been shown that the proposed topology reduces power loss in the switches. Based on a survey of the existing literature on SCMLIs, the following use cases have been identifed for the proposed topology: 6.3.1. High-Frequency AC Distribution. Due to the signifcant reduction in the number of power conversion stages, the size of the transformer, and the size of the flter, a highfrequency alternating current (HFAC) power distribution system (PDS) has gained popularity in high-power density applications such as telecommunication [36,37], spacecraft, and computer systems [38]. Another emerging feld for HFAC PDS is its use in localised networks, such as     microgrids, buildings, and electric vehicles [39]. Te use of magnetic circuits or dc-dc boost converters can be avoided in low voltage regions when SCMLI topologies are implemented.  a step-up transformer can all be used to increase the voltage. Tese methods raise the bar in terms of complexity, expense, footprint, and energy waste [40]. However, SCMLIs ofer grid compatibility, a high-resolution waveform, reduced fltering needs, and increased voltage gain [41,42]. Cascading the cells in EV systems is one way to get a high dc-link voltage, although charge balancing is a problem [43][44][45]. To circumvent these limitations of conventional EV drives, SCMLIs are being developed as a practical interface for converting low-voltage dc to high-voltage ac [45,46].

Conclusion
Tis article describes a revolutionary SC-based boost-type seven-level inverter. Te proposed SC-MLI topology's primary objective is to minimize switching components in order to achieve a high gain and with eight switching components and single isolated DC source seven levels are obtained in the output voltage profle. Additionally, the proposed converter output voltage is 3 times that of an input supply voltage, and capacitors are naturally self-balanced. Te mathematical modelling of proposed topology is presented and validated with simulated results. Efciency and loss investigation of the proposed MLI topology are presented and compared the same through the recent literature available on SC-MLI topologies. A brief comparative study has been carried out to check the superiority of other SC topologies in component count per level, MBV, and gain of the converter. Tis analytical comparison makes the proposed work more competitive and prominent. In the end, the experimental and simulated results for linear and nonlinear loads empower the fndings of the study and reveal the practicality of the suggested design topology. Proposed SC-MLI topology performance was good at dynamic linear and nonlinear loads and with dynamic modulation index.

Data Availability
No underlying data were used to support the fndings of this study.

Conflicts of Interest
Te authors declare that they have no conficts of interest.