ITE Technical Report
Online ISSN : 2424-1970
Print ISSN : 1342-6893
ISSN-L : 1342-6893
40.12 Information Sensing Technologies(IST)
Session ID : IST2016-15
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A 1.2e- Temporal Noise 3D-Stacked CMOS Image Sensor with Comparator-Based Multiple Sampling PGA
Kei SHIRAISHIYasuhiro SHINOZUKATomonori YAMASHITAKazuhide SUGIURANaoto WATANABERyuta OKAMOTOTatsuji ASHITANIMasanori FURUTATetsuro ITAKURA
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Abstract

This paper presents a 1.2e-, power efficient 8Mpixel, 3D-stacked CMOS image sensor (CIS) for mobile applications. The proposed CMOS image sensor (CIS) composed of low-noise PGA and low power SS-ADC. PGA is realized with comparator-based switched-capacitor architecture with a multiple sampling technique to reduce the temporal noise at high gain. To further reduce the power consumption, SS-ADC with look-ahead scheme is proposed to turn off the unnecessary power consumption. The developed CIS achieves FoM of 5.97nW*e-/pixel/s with temporal noise of 1.2e- at 20fps at 32-times sampling.

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© 2016 The Institute of Image Information and Television Engineers
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