Hawkeyes: Addressing Weak Memory Order in Program Migration Based on Instruction Windows

Migrating memory systems from x86 to ARM can result in weak memory order issues due to memory model differences. This necessitates the addition of memory barriers to prevent such problems. However, current automatic memory barrier insertion approaches fail to identify all potential locations where WMM (Weak Memory Model) bugs may occur and also often overuse unnecessary memory barriers. To address this issue, we propose Hawkeyes, an approach that combines dynamic memory access conflict detection and instruction windows to locate out-of-order memory access issues in multi-threaded programs. Hawkeyes performs compile-time instrumentation to locate all memory conflicts at run time and analyzes the micro-instructions together with the instruction window to identify out-of-order instruction intervals. By comparing such intervals among different threads, Hawkeyes determines the locations that need to maintain order. We validate the correctness of Hawkeyes on open-source libraries and evaluate Hawkeyes on public benchmarks. We demonstrate that Hawkeyes not only pinpoints all the locations where WMM bugs may appear but also achieves high accuracy in barrier insertion.