Construction of All Multilayer Monolithic RSMTs and Its Application to Monolithic 3D IC Routing

2.1 Terminologies

2.1.1 2D Hanan Grid.

Suppose a finite set S of points is given in the 2D plane. Let \(X_S = \lbrace x_1,\ldots ,x_L\rbrace ~(x_1 \le \cdots \le x_L)\) and \(Y_S = \lbrace y_1,\ldots ,y_M\rbrace ~(y_1 \le \cdots \le y_M)\) be the sets of the x- and y-coordinates of the points in S, respectively. Then, the 2D Hanan grid constructed for S is a graph \(G_S=(V_S,E_S),\) where \(V_S\) and \(E_S\) are defined as follows: \(\begin{eqnarray*} V_S=\lbrace (x, y) | x \in X_S, y \in Y_S\rbrace , E_S = E_{S,X} \cup E_{S,Y}, \\ E_{S,X} = \lbrace (v_1,v_2) | v_1=(x_i,y_j) \in V_S, v_2=(x_{i+1},y_j) \in V_S\rbrace , \\ E_{S,Y} = \lbrace (v_1,v_2) | v_1=(x_i,y_j) \in V_S, v_2=(x_i,y_{j+1}) \in V_S\rbrace . \end{eqnarray*}\) Figure 2(a) shows the 2D Hanan grid constructed for the five points, \(\lbrace p_1,\ldots , p_5\rbrace\).

Fig. 2.

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2.1.4 Potentially Optimal Wirelength Vector and POST.

The wirelength of an RST on the 2D Hanan grid can be expressed as a linear combination of the x- and y-directional edge vectors representing the tree as explained in the work of Chu and Wong [2]. For example, the wirelength of the tree in Figure 3(a) is (1) \(\begin{equation} L = 1 \cdot h_1 + 2 \cdot h_2 + 2 \cdot h_3 + 1 \cdot h_4 + 1 \cdot v_1 + 1 \cdot v_2 + 1 \cdot v_3 + 1 \cdot v_4, \end{equation}\) which can also be expressed as \(L = C \cdot E,\) where \(C = (1,2,2,1,1,1,1,1)\) and \(E = (h_1,h_2,h_3,h_4,v_1,v_2,v_3,v_4)\). C is called a coefficient vector and E is called an edge length vector. The edge length vector is a constant vector for given pins. However, the coefficient vector is dependent on the RST. For example, the coefficient vector for the tree in Figure 3(b) is \((1,2,1,1,1,1,2,1)\). Thus, the two trees in Figure 3 have the same edge length vector but different coefficient vectors.

Fig. 3.

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For given pin locations, a coefficient vector \(C=(c_1,\ldots , c_k)\) becomes a Potentially Optimal Wirelength Vector (POWV) if it satisfies the following conditions [2]:

•	There exists an RST that connects all the pins and uses the edges specified in the coefficient vector C on the Hanan grid constructed for the pins.
•	There is no other coefficient vector \(C^{\prime }=(c_1^{\prime },\ldots , c_k^{\prime })\) satisfying \(c_i^{\prime } \le c_i\) for all \(i=1,\ldots ,k\).

An RST corresponding to a POWV is called a potentially optimal Steiner tree (POST) [2]. The two RSTs shown in Figure 3(a) and (b) are POSTs.

2.2 Construction of All RSMTs on the Hanan Grid

FLUTE constructs an RSMT by a lookup table [2]. The lookup table consists of all PSs, all POWVs belonging to each PS, and one POST for each POWV. Whenever a set of pin locations is given, FLUTE first finds the PS of the pin locations, compares the wirelengths of all the POWVs belonging to the PS, and returns the POST of the POWV having the minimum wirelength. If multiple POWVs have the same wirelength, FLUTE can return their POSTs. The returned POSTs are RSMTs for the pin locations. However, FLUTE finds only one POST for each POWV, although a POWV can have multiple POSTs. Thus, Lin generated a DB (called ARSMT DB) storing all POSTs for each POWV in previous work [9, 12]. Figure 4 shows an overview of the ARSMT DB. The algorithm finding all POSTs for each POWV uses a binary decision tree with several speedup techniques to reduce the DB construction time.

Fig. 4.

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2.3 Multilayer Monolithic Rectilinear Steiner Minimum Trees

We first define three terminologies.

The wirelength of a 3D rectilinear tree is computed by the sum of the lengths of all the edges in the tree. In the M3D IC layout design, however, the area and capacitance overhead of an MIV is negligible, so we can set the length of an MIV (the length of a z-directional edge) to zero during 3D routing. However, minimizing the number of MIVs inserted in the layout is still crucial. Thus, we define an MMRSMT as follows.

If we project all the edges in an MMRSMT onto the xy plane, the projection becomes a 2D RSMT. Thus, an MMRSMT can be constructed from a 2D RSMT by properly placing the x- and y-directional edges of the 2D RSMT in a 3D grid and inserting z-directional edges. In addition, we obtain 2D RSMTs from POSTs as mentioned in the previous section. Thus, we can construct an MMRSMT from a POST. We define a 3D POST as follows.

In summary, if we have a DB of all 3D POSTs, we can build all MMRSMTs for given pin locations quickly. In this work, therefore, we build a DB of all 3D POSTs for all possible relative pin locations in two, three, and four tiers. Note that in the case of pins without unique x- or y-coordinates, we can assume they have distinctive coordinates by slightly adjusting their locations to the left/right (for x-coordinates) or up/down (for y-coordinates). Based on that, we generate PSs from their relative positions knowing that the lengths of the newly evolved edges (tiny extensions) are zeros. This would eventually revert the distinct coordinates to their actual nondistinct coordinates.

3.1 Construction of All 3D POSTs

The input to the algorithm is a set P of pin locations and a 2D POST, \(G_2 = (V_2, E_2)\), constructed from the projection of the pins onto the xy plane. For example, Figure 6(a) shows three pins in a 3D grid, the projection of the pins, and a 2D POST for them.

Fig. 6.

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Algorithm 1 shows the proposed algorithm for constructing all 3D POSTs. We first set the visited variables of all the edges in \(E_2\) to false (line 1). Then, we sort the edges and store the result in an ordered set \(E_2^{\prime }\) (line 2). The sort_edges function chooses a pin vertex in \(G_2\) and performs the breadth-first search starting from the vertex until all the pin vertices are reached. Whenever it goes through an edge, the function inserts the edge into \(E_2^{\prime }\). This order reduces the runtime of the algorithm. For example, the sort_edges function starts from the pin vertex \(p_1\) in Figure 6(a). Then, \(E_2^{\prime }\) becomes \((e_x(0,0), e_y(0,1), e_x(1,1), e_y(1,1))\). Then, we construct a 3D grid \(G_3=(V_3,E_3)\) from \(G_2\) and P (line 3). The construct_3D_grid function expands \(G_2\) to \(G_3\) as shown in Figure 6(b). Then, we set the used variables of all the edges in \(E_3\) to false (line 4). T is a set of graphs storing all the 3D POSTs, nr_MIVs is a variable storing the number of MIVs used in \(G_3\), and min_nr_MIVs is a variable storing the minimum number of MIVs used in the 3D POSTs (line 5). Then, we call the recur_con function to recursively construct all 3D POSTs (line 6). Once the algorithm ends, we return T (line 7).

The recur_con function starts from checking the given index, which is used to access the edges in \(E_2^{\prime }\). The edge index is greater than the number of edges in \(E_2^{\prime }\) when there is no more edge to process in \(G_3\) (line 1), which means that \(G_3\) is a 3D graph connecting all the pins. In this case, if the total number of MIVs used in \(G_3\) is equal to the minimum number of MIVs used in the best graphs found until now, we add it to T (line 3). However, if the total number of MIVs used in \(G_3\) is less than the minimum number of MIVs used in the best graphs found until now, all the graphs in T use more MIVs than \(G_3\), so we empty T, add \(G_3\) to T, and update min_nr_MIVs (line 5).

If the edge index is less than the size of \(E_2^{\prime }\) (line 9), we visit the edge in \(E_2^{\prime }\) indexed by the edge index variable (line 10) and try using edges in \(G_3\) corresponding to the indexed edge (lines 11–31). First, suppose \(e_d^{\prime }(i,j)\) is \(E_2^{\prime }\)[index], where d is either x or y. Then, we try using \(e_d(i, j, k)\) in \(G_3\) for each \(k=0,\ldots ,t-1\) (line 13). In Figure 6(c), for example, we try using \(e_x(0,0,0)\) in \(G_3\). Then, if e is x-directional, we obtain its left vertex in \(G_2\), and otherwise we obtain its bottom vertex in \(G_2\) and assign it to v (line 14). Then, we find the bottommost and topmost tiers that should be connected along the z-axis through v in \(G_3\) by the get_min_max_tier function (lines 15–18). The function finds all the visited edges connected to e in \(G_2\), obtains the tiers of the edges in \(G_3\) corresponding to the visited edges, and finds the bottommost and topmost tiers. In addition, if v is a pin vertex, its z-coordinate should be included in the computation of the range of the tiers. We repeat the same process for the right vertex of e (or the top vertex if e is y-directional) (lines 19–23).

If we have visited all the edges connected to the left and right (or the bottom and top) vertices of e, we can find the z-directional edges required to connect to the pin and the edges along the z-axis at the vertices. From the z-directional edges, we obtain the number of MIVs (line 24). If the total number of MIVs currently used in \(G_3\) is less than or equal to the minimum number of MIVs used in the best graphs found until now, we move on to the next edge in \(E_2^{\prime }\) (line 27). Otherwise, the current graph uses more MIVs than the best graphs, so we do not need to proceed to the next edge. Once the recursive function call ends (line 28), we re-adjust the number of MIVs used in \(G_3\) (line 29) and try using the edge above e (lines 30 and 31).

In Figure 6(c), for example, \(e_x(0,0,0)\) is in Tier 0 and its left vertex is a pin vertex, so both the bottommost and topmost tiers for the vertex are Tier 0. Then, we move on to \(e_y(0,1)\) in \(E_2^{\prime }\) and try using \(e_y(0,1,0)\) in \(G_3\) in Figure 6(d). The used variables of all the edges connected to the bottom vertex of \(e_y(0,1)\) are true at this point and all the edges are placed in Tier 0. Thus, we do not need to add any z-directional edges above the vertex. Then, we process the next edge \(e_x(1,1)\) in Figure 6(e). The right vertex of \(e_x(1,1)\) is connected to the pin located at \((2,1)\) in \(G_2\), which corresponds to the pin located at \((2,1,1)\) in \(G_3\), so the bottommost and topmost tiers at the vertex are Tier 0 and Tier 1, respectively. Thus, we use \(e_z(2,1,0)\) in \(G_3\), which is inserting an MIV into the location. When we also try using \(e_y(1,1,0)\) in Figure 6(f), we finally construct a 3D graph connecting all the pins and the total number of MIVs is 3. Similarly, the total numbers of MIVs in the 3D graphs in Figure 6(g) through (i) are all 3. However, the 3D graph in Figure 6(j) uses two MIVs. At this time, T contains all the 3D graphs found in Figure 6(f) through (i), so we delete all of them from T and add the 3D graph found in Figure 6(j) to T. There are four more 3D graphs using two MIVs as shown in Figure 6(k) through (n). Thus, when the algorithm finishes, T contains all the five 3D graphs, which become 3D POSTs for the given pin locations and 2D POST.

3.2 Congruence of 3D POSTs

The runtime of the algorithm shown in Algorithm 1 is still long and there are numerous 3D POSTs in the DB, so it is crucial to reduce the runtime and the DB size. In this section, we show congruent properties of the 3D POSTs, which are used to skip generating and storing some 3D POSTs.

3.2.1 Congruence of PSs.

As mentioned in the work of Chu and Wong [2], two PSs are congruent if rotating one of them leads to the other. For example, Figure 7(a) shows the PS \((3 1 5 4 2)\). If we rotate it counterclockwise by 90, 180, and 270 degrees, we obtain PSs \((4 1 5 2 3)\), \((4 2 1 5 3)\), and \((3 4 1 5 2)\) as shown in Figure 7(b), (c), and (d), respectively. If two PSs are congruent to each other, the POSTs constructed for one of them can be used for the other. Thus, we do not need to generate 2D POSTs for some PSs. In addition to the rotation, reflection also generates congruent PSs. Reflecting the pin locations in Figure 7(a) over the y-directional line results in PS \((3 5 1 2 4)\) shown in Figure 7(e). Now, rotating the PS counterclockwise by 90, 180, and 270 degrees leads to PSs \((3 2 5 1 4)\), \((2 4 5 1 3)\), and \((2 5 1 4 3)\) shown in Figure 7(f), (g), and (h), respectively.

Fig. 7.

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Rotating and reflecting a PS has the same effect as generating PSs by \(\Gamma _{(s,r)}\). For example, generating the PS in Figure 7(a) is the same as generating the PS \(\Gamma _{(y_+,x_+)}\). The PSs obtained by rotating the PS \(\Gamma _{(y_+,x_+)}\) by 90, 180, and 270 degrees are the same as the PSs \(\Gamma _{(x_+,y_-)}\), \(\Gamma _{(y_-,x_-)}\), and \(\Gamma _{(x_-,y_+)}\), respectively. Similarly, reflecting \(\Gamma _{(y_+,x_+)}\) over the y-directional line is the same as generating the PS \(\Gamma _{(y_+,x_-)}\). Then, rotating \(\Gamma _{(y_+,x_-)}\) by 90, 180, and 270 degrees is the same as obtaining the PSs \(\Gamma _{(x_-,y_-)}\), \(\Gamma _{(y_-,x_+)}\), and \(\Gamma _{(x_+,y_+)}\), respectively. Appendix A shows operations defined for PSs, their properties, and a table for the congruence rules.

If multiple PSs are congruent, we store POSTs for only one (called a base position sequence) of them. Then, we can obtain POSTs for the other PSs by properly transforming the POSTs stored for their base PS. We use the following rule to determine base PSs. When pin locations are given, we find eight PSs \(\Gamma _{(y_\pm ,x_\pm)}\) and \(\Gamma _{(x_\pm ,y_\pm)}\) for them and choose the smallest PS for its base PS. In Figure 7, for example, \((2 4 5 1 3)\) in Figure 7(g) is the smallest number, so \((2 4 5 1 3)\) becomes the base PS for all the PSs in Figure 7.

3.2.2 Congruence of 3D POSTs.

Suppose pin locations are given in the 3D space. Then, we can characterize the pin locations by two sequences: a PS and a Tier Sequence (TS). The PS is based on the projection of the pins onto the xy plane, and the TS is based on the z-coordinates of the pins. Figure 8 shows an example. In Figure 8(a), the z-coordinates of the pins corresponding to the PS elements 3, 1, 5, 4, 2 are 0, 1, 0, 1, 0, respectively. Thus, the TS for the pin locations is \((0 1 0 1 0)\).

Fig. 8.

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If we rotate the two tiers in Figure 8(a) counterclockwise by 90, 180, and 270 degrees around the z-axis, we obtain the PSs and TSs shown in Figure 8(b), (c), and (d), respectively. In addition, if we reflect the two tiers in Figure 8(a) over the yz plane, we obtain the PS and TS in Figure 8(e). Rotating the two tiers in Figure 8(e) counterclockwise by 90, 180, and 270 degrees around the z-axis leads to the PSs and TSs in Figure 8(f), (g), and (h), respectively. Moreover, reflecting the two tiers in Figure 8(a) and (e) over the xy plane generates the PSs and TSs in Figure 8(i) and (m), respectively. Rotating them counterclockwise by 90, 180, and 270 degrees around the z-axis generates the PSs and TSs in Figure 8(j), (k), and (l), and Figure 8(n), (o), and (p), respectively.

To find a congruence between two sets of PSs and TSs, we define a 3D position sequence \(\Lambda _{(s,r,w)}\), which consists of a pair of sequences. The first sequence is the 2D PS \((a_1 ... a_n)\) obtained from \(\Gamma _{(s,r)}\). The second sequence is the TS along the w-direction (\(w \in \lbrace z_+,z_-\rbrace\)) as defined previously. Then, the 3D PS for the pins in Figure 8(a) is denoted by \(\Lambda _{(y_+,x_+,z_+)}\). Similarly, 3D PSs for the pins in Figure 8(b), (c), (d), (e), (f), (g), and (h) are \(\Lambda _{(x_+,y_-,z_+)}\), \(\Lambda _{(y_-,x_-,z_+)}\), \(\Lambda _{(x_-,y_+,z_+)}\), \(\Lambda _{(y_+,x_-,z_+)}\), \(\Lambda _{(x_-,y_-,z_+)}\), \(\Lambda _{(y_-,x_+,z_+)}\), and \(\Lambda _{(x_+,y_+,z_+)}\), respectively. Since the reflection over the xy plane reverses the TS, 3D PSs for the pins in Figure 8(i), (j), (k), (l), (m), (n), (o), and (p) are \(\Lambda _{(y_+,x_+,z_-)}\), \(\Lambda _{(x_+,y_-,z_-)}\), \(\Lambda _{(y_-,x_-,z_-)}\), \(\Lambda _{(x_-,y_+,z_-)}\), \(\Lambda _{(y_+,x_-,z_-)}\), \(\Lambda _{(x_-,y_-,z_-)}\), \(\Lambda _{(y_-,x_+,z_-)}\), and \(\Lambda _{(x_+,y_+,z_-)}\), respectively. If two sets of pin locations are congruent, we can use the 3D POSTs belonging to one of them for the other by properly transforming the 3D POSTs.

We also define a 3D base position sequence as follows. Suppose a set of pin locations is given in the 3D space. Then, we find all the 16 3D PSs \(\Lambda _{(y_\pm , x_\pm , z_\pm)}\) and \(\Lambda _{(x_\pm , y_\pm , z_\pm)}\) for them and choose the smallest 3D PS for their 3D base PS. If multiple 3D PSs have the same 2D PS, the one with the smallest TS becomes the 3D base PS for them. In Figure 8, for example, the smallest 2D PS is \((2 4 5 1 3)\) in Figure 8(g) and (o). Between these two, the TS \((0 1 0 1 0)\) is smaller than the TS \((1 0 1 0 1)\), so the 3D PS of Figure 8(g) becomes the 3D base PS for all the 3D PSs in Figure 8. Appendix A also shows operations defined for 3D PSs, their properties, and a table for the congruence rules.

5.1 Motivation

Figure 10 shows a two-tier 3D placement result for a five-pin net to be routed. The 3D PS is \(\Lambda _{(y_+,x_+,z_+)} = ((31542), (00011)),\) and the POWV is \((12211111)\). If we assume the length of each planar edge is l and the length of an MIV is \(l_m\), then all 3D POSTs in the figure have the same length of \((10l+l_m)\).

Fig. 10.

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Suppose the source of the net is \(p_5\) and the critical sink (the sink that has the smallest slack) is \(p_4\). Then, the SCSL is \((2l+l_m)\) in Figure 10(a), but that in Figure 10(b) is \((4l+l_m)\), so the former has a shorter SCSL. Similarly, suppose the source is \(p_2\) and the critical sink is \(p_4\). Then, all the topologies in Figure 10 have the same SCSL of 3l. We can also compute the SCSD using the PI model for the edges and the Elmore delay model for the delay estimation. Suppose the output resistance of the source is \(R_D\), the input capacitance of each sink is \(C_L\), the RC of an edge are r and c, respectively, and the RC of an MIV are \(r_m\) and \(c_m\), respectively. Then, if the source is \(p_5\) and the critical sink is \(p_4\), the SCSD in Figure 10(a) is smaller than that in Figure 10(b) by \(r(5C_L + 9c + c_m)\). Moreover, the two topologies in Figure 10(a) have the same 2D projection with different MIV locations. Thus, the topology on the left has less SCSD than the one on the right if \((\frac{r}{c} \lt \frac{r_m}{c_m})\), whereas the right one has less SCSD if \((\frac{r}{c} \gt \frac{r_m}{c_m})\). In addition, if the source is \(p_2\) and the critical sink is \(p_4\), the SCSD of the topologies in Figure 10(b) is smaller than that in Figure 10(a) by \(r(3C_L + 7c + c_m)\) as shown in Table 2. In conclusion, the effectiveness of a particular topology for a specific metric is dependent on the locations of the source and sinks and can be maximized only after examining all the MMRSMTs.

5.2 Simulation Methodology

To show the effectiveness of the use of the ARD, we compare two 3D routing topology generation approaches. The first is a so-called BF approach that selects one MMRSMT for each 3D net. If a 3D net is given, we select the first MMRSMT found in the ARD for the pin locations of the 3D net. The second approach is using the ARD for which we search the ARD for a given 3D net, find all MMRSMTs, and select the best one for a given metric (SCSL or SCSD). We used the ISPD 2005 and 2006 benchmarks [16, 17] and ePlace-3D [15] to generate 3D placement results in two, three, and four tiers. For the SCSD computation, we assume that the output resistance of a source (driver) is \(100 \Omega\), the wire RC per unit length are \(2 \Omega\)/unit and \(0.4fF\)/unit, respectively, and the load capacitance of a sink pin is 5fF [12]. The MIV height, resistance, and capacitance are 140 nm, \(4 \Omega\), and 1fF, respectively [7, 18]. For each 3D net, we set the source pin to the driver node of the net from the benchmark suites, randomly selected a pin for the critical sink, constructed two 3D routing topologies, one by the BF approach and the other by the ARD, and compared their SCSLs and SCSDs.

5.3 Simulation Results

Table 3 shows the comparison of the SCSLs of the 3D routing topologies constructed by the BF- and ARD-based approaches for all the 3D nets of the benchmarks with net degree 4 and 6. Notice that all 2D POSTs for each two- or three-pin net have the same SCSL regardless of the selection of the source and critical-sink pins. Therefore, the 3D routing topologies constructed for these nets by BF and ARD have the same SCSL. The BF and ARD have different SCSLs for approximately \(20.70\%\) to \(23.54\%\) of the 3D nets (\(N_L/N\)). Nonetheless, the average SCSL differences (\(L_T/N_L\)) between BF and ARD are approximately 103, 92, and 86 for the two-, three-, and four-tier designs, respectively. Moreover, we compute the sum of the ratios of each SCSL difference to its average to obtain the average difference ratio, which are 0.09, 0.11, and 0.14, respectively, for the two-, three-, and four-tier designs. The maximum SCSL differences are also very large (840 to 7,080), so the comparison shows that ARD can effectively minimize the SCSL for each 3D net.

We also observe that the average SCSL difference (\(L_T/N_L\)) between BF and ARD generally goes down as the tier count goes up from 2 to 4. This is because stacking more tiers helps reduce the wirelength of each net. For example, the uniform-scaling-based 3D placement [1, 13] ideally reduces the wirelength of a net by \(1/\sqrt {t}\), where t is the number of tiers. As a result, the average SCSL difference also goes down as the tier count increases. However, the maximum SCSL difference is dependent not only on the 3D placement result but also on whether the 3D routing topologies constructed by BF can minimize the SCSLs by accident. Thus, the maximum SCSL difference does not go down even if the tier count goes up as shown in the table.

We observe similar trends in the SCSD simulation results. First of all, BF and ARD have different SCSDs for approximately \(53.28\%\) to \(57.40\%\) of the 3D nets (\(N_D/N\)). The reason that \(N_D/N\) is greater than \(N_L/N\) is that two 3D routing topologies with the same SCSL can have different SCSDs as shown in Figure 10 and Table 2. The average SCSD differences (\(D_T/N_D\)) between BF and ARD are approximately 222ps, 195ps, and 122ps for the two-, three-, and four-tier designs, respectively. The maximum SCSD differences are also large as shown in the table. Moreover, the SCSD average difference ratios are 0.14, 0.15, and 0.17, respectively, for the two-, three-, and four-tier designs. Although several interconnect optimization techniques such as buffer insertion would help reduce the SCSD, finding a good 3D routing topology would still be one of the most important interconnect optimization techniques. As shown previously, the ARD can provide multiple 3D routing topologies optimal for different metrics such as SCSL and SCSD.

Note that in some cases, minimizing the SCSL (or SCSD) of a net may not be compatible with constructing its RSMT. As the papers related to this work [2, 12] aimed at minimizing the planar wirelength (and then minimizing # vertical edges), we do not construct minimum-SCSL (or minimum-SCSD) topologies either. Instead, we find topologies minimizing the SCSL (or SCSD) among the MMRSMTs for a given net.

6.1 Simulation Methodology

We used ePlace-3D [15] for 3D placement and bin-based 3D global routing for the congestion-aware 3D routing. Each x- or y-directional edge \(e_{c,i,j,k}\) (\(c \in \lbrace x, y\rbrace\)) has a predetermined maximum capacity \(m_{c,i,j,k}\) and the # nets \(s_{c,i,j,k}\) crossing the edge. Similarly, each bin \(bin_{z,i,j,k}\) has a predetermined maximum MIV capacity \(m_{bin,i,j,k}\) and the # MIVs \(s_{bin,i,j,k}\) located on that bin. We compute the overflow \(OF_{c,i,j,k}\) (or \(OF_{bin,i,j,k}\)) of edge \(e_{c,i,j,k}\) (or bin \(bin_{z,i,j,k}\)) as follows: (5) \(\begin{equation} OF_{w,i,j,k} = {\left\lbrace \begin{array}{ll} (s_{w,i,j,k} - m_{w,i,j,k}), & \text{if $s_{w,i,j,k} \gt m_{w,i,j,k}$} \\ 0, & \text{otherwise} \end{array}\right.} \end{equation}\) where \(w \in \lbrace c, bin\rbrace\). The objective is to minimize the total overflow in the following equation while routing all the 2D and 3D nets sequentially. (6) \(\begin{equation} OF_{Combined} = \alpha \cdot OF_{c,i,j,k} + \beta \cdot OF_{bin,i,j,k} \end{equation}\)

We chose \(\alpha\) and \(\beta\) suitably. We estimate the maximum MIV capacity of a bin by deducting the total area occupied by all instances of that bin from the total bin area and dividing the resulting area by the MIV pitch area. Moreover, MIV violations occur when the number of MIVs placed in a bin exceeds its maximum MIV capacity.

We route all the 2D and 3D nets of each design using two routing methodologies similar to the BF- and ARD-based routing methodologies used in Section 5. We route each net as follows:

However, we made an exception for the six-pin-four-tier case and used the net-breaking technique shown in the following for both the BF and ARD due to memory limitations. Moreover, we also routed all the nets of each design using MLOARST construction algorithms [8] to assess the efficacy of the ARD-based routing approach.

Note that global routing is a coarse-level bin-based routing step focusing on constructing routing topologies for a given design on a single routing layer under maximum capacity constraints. On the contrary, detailed routing that includes track assignment is a more fine-grained routing step based on the routing topologies obtained in the global routing step. In brief, since a single routing layer is often used for global routing purposes in the literature, we also consider similar conventions and problem definitions in this research.

6.2 3D Net-Breaking Techniques

Suppose N pins of a 3D net, \(P = \lbrace p_1, p_2,\ldots , p_N\rbrace\), are given and its 3D PS is \(((s_1 s_2 ... s_N), (t_1 t_2 ... t_N))\). If a group of the pins belongs to an octant and the others belong to its opposite octant, we can break the pins into two groups, construct an MMRSMT for each group, and connect the two MMRSMTs using an additional point. Figure 11(a) illustrates the octant pairs geometrically opposite in the 3D space. For example, if \(P_{G1} = \lbrace p_1,\ldots , p_r\rbrace\) belongs to the octant \(x_+y_+z_+\) and \(P_{G2} = \lbrace p_{r+1},\ldots , p_N\rbrace\) belongs to the opposite octant \(x_-y_-z_-\), we can find \(p_i \in P_{G1}\) and \(p_j \in P_{G2}\) closest to the origin. Then, we can insert a point \(p_h\) in the hexahedron constructed with \(p_i\) and \(p_j\) as the two endpoints of the hexahedron. Then, the union of the two MMRSMTs constructed for \(P_{G1} \cup \lbrace p_h\rbrace\) and \(P_{G2} \cup \lbrace p_h\rbrace\) is an MMRSMT for P. Figure 11(b) through (e) demonstrate the four octant pairs, (\(x_{-}y_{-}z_{-}\rightarrow x_{+}y_{+}z_{+}\)), (\(x_{-}y_{-}z_{+}\rightarrow x_{+}y_{+}z_{-}\)), (\(x_{+}y_{-}z_{-}\rightarrow x_{-}y_{+}z_{+}\)), and (\(x_{+}y_{-}z_{+}\rightarrow x_{-}y_{+}z_{-}\)), that can be used for 3D optimal net breaking.

Fig. 11.

View Figure

Let \(S_{G1}\) and \(S_{G2}\) be the PS values of \(P_{G1}\) and \(P_{G2}\), respectively. Similarly, let \(T_{G1}\) and \(T_{G2}\) be the TS values of \(P_{G1}\) and \(P_{G2}\), respectively. Then, the following inequalities show the conditions for the 3D optimal net breaking: (7) \(\begin{eqnarray} \mathrm{max}(S_{G1}) \le \mathrm{min}(S_{G2}) \ \ \& \ \ \mathrm{max}(T_{G1}) \le \mathrm{min}(T_{G2}), \end{eqnarray}\) (8) \(\begin{eqnarray} \mathrm{max}(S_{G1}) \le \mathrm{min}(S_{G2}) \ \ \& \ \ \mathrm{min}(T_{G1}) \ge \mathrm{max}(T_{G2}), \end{eqnarray}\) (9) \(\begin{eqnarray} \mathrm{min}(S_{G1}) \ge \mathrm{max}(S_{G2}) \ \ \& \ \ \mathrm{max}(T_{G1}) \le \mathrm{min}(T_{G2}), \end{eqnarray}\) (10) \(\begin{eqnarray} \mathrm{min}(S_{G1}) \ge \mathrm{max}(S_{G2}) \ \ \& \ \ \mathrm{min}(T_{G1}) \ge \mathrm{max}(T_{G2}), \end{eqnarray}\) where \(\mathrm{max}(A)\) and \(\mathrm{min}(A)\) find the maximum and minimum elements in A, respectively, and Inequalities (7) through (10) correspond to the cases shown in Figure 11(b) through (e), respectively. The figures also show new Steiner points () inserted for the 3D optimal net breaking. Note that in Figure 11(b) through (e), dots in red (), cyan (), green (), and black () indicate nodes on Tiers 3, 2, 1, and 0, respectively.

Notice that a 3D net cannot be optimally broken if we cannot find \(P_{G1}\) and \(P_{G2}\) satisfying any of the inequality pairs in (7) through (10). In this case, we first project all the pins of the 3D net onto the xy plane and perform 2D optimal net breaking for the projected pins. If this is successful, there will be two groups of the projected pins, so we construct an MMRSMT for each pin group and connect the two MMRSMTs. If this is not successful, however, we use the 2D net-breaking heuristics for the projected pins [2], construct an MMRSMT for each pin group, and connect all the MMRSMTs.

6.3 Simulation Results

Table 4 compares the planar overflows and the number of MIV violations of the congestion-aware 3D global routing by the BF- and ARD-based routing. The number of global nets shows the total number of nets routed optimally (by 2D RSMTs and MMRSMTs) or nonoptimally, whereas the number of routed nets shows the total number of nets routed optimally. For all the designs, most of the nets (around 94% on average) are routed optimally because they are low-degree nets. Table 5 shows the details of the # “k-Pin” nets for each “k.”

For the two-tier designs, the ratios of the total number of planar overflows and MIV violations between BF and ARD are 0.25 and 0.47 on average, respectively, which demonstrate that the use of ARD can reduce the routing congestion effectively. ARDs are effective because they minimize planar overflow while distributing MIVs according to available whitespace. For each net, the minimum planar wirelength is used and then MIVs are minimized. The average planar overflows (# planar overflows per edge capacity) and the maximum planar overflows of ARD are also lower than those of BF by 48% to 93% and 11% to 74%, respectively. Furthermore, the # MIV violations of ARD is 20% to 68% fewer than their BF counterparts. Note that a higher number of tiers means more bins accepting MIVs, which boosts the overall capacity of MIVs. Consequently, we expect fewer MIV violations. Nevertheless, the # MIVs will also rise due to the increasing number of 3D wires. Thus, with more tier inclusion, the # MIV violations varies either way (increasing or decreasing).

The runtime of the BF approach is less than 1 second for small benchmarks and maximum 2 seconds for the largest design. However, ARD takes 4 to 30 seconds for the routing of all the nets. The runtime overhead is negligible, but the overflow reduction is significantly large, which shows the effectiveness of the ARD for the routing congestion minimization. We observe similar trends in the three- and four-tier designs. The planar overflow ratio between the BF and ARD designs is 0.24 for the three-tier designs and 0.27 for the four-tier designs on average provided 49% less MIV violations on average for both the cases. ARD still achieves 11% to 83% lower maximum planar overflows with 38% to 63% fewer MIV violations for the three-tier designs and 29% to 69% lower maximum planar overflows with 38% to 68% fewer MIV violations for the four-tier designs.

Table 6 compares the planar overflows and the number of MIV violations of congestion-aware 3D global routing by the MLOARST construction algorithms (denoted by MR) and ARD-based routing. For the two-, three-, and four-tier designs, the ratios of the total number of planar overflows between MR and ARD are 0.26, 0.25, and 0.25 on average, respectively, and are 0.18, 0.16, and 0.16 on average, respectively, for the number of MIV violations. ARD’s average and maximum planar overflows are consistently lower with significantly fewer # MIV violations compared to MR. This is because even with the minimized planar wirelength and MIV count, the MR only generates one routing topology demonstrating the effectiveness of ARD with multiple topologies to reduce routing congestion. However, only for the four-tier bigblue2 design, the ARD shows slightly more planar and maximum overflow than MR. This is because nets were sequentially routed in the ARD. Routing topologies were chosen to minimize the total overflow that ultimately depends on the net routing order. Still, the # MIV violations are significantly fewer for ARD compared to MR.

Moreover, Table 7 shows a detailed comparison of the # 3D nets, the total Half-Perimeter Wirelength (HPWL), the MIV distribution on different tiers, and the total # MIVs for the two-, three-, and four-tier designs for all the benchmarks. Except for adaptec4 and bigblue3, the number of 3D nets increases as the tiers climb. The total HPWL is computed from the HPWL of the 2D nets plus the 2D projection of the 3D nets. The HPWL decreases from the two-tier design to the four-tier design for all the benchmarks except for adaptec2, bigblue3, newblue2, and newblue5, which is purely dependent on the placement locations of the instances. We obtained the placement results from the 3D placer [15] that showed a similar trend to the HPWL as well. Note that all the routed designs have a minimum planar wirelength. Furthermore, the number of MIVs increases from two-tier to three-tier designs and from three-tier to four-tier designs except for the adaptec4 and bigblue3 benchmarks. The reason is that the three-tier designs have more 3D nets than the four-tier designs for these benchmarks discussed earlier. Ideally, the # MIVs should exceed the # 3D nets. Moreover, in most cases, two-tier nets dominate the set of 3D nets. The MIV distribution on each tier is therefore related to the 3D net distribution on that tier to its lower neighboring tier.

In conclusion, controlling the MIV density is crucial for the MIV violations, which are not trivial, and should be considered after minimizing the planar wirelength for the congestion-aware 3D global routing. In addition to that, by integrating our ARD into the ePlace-3D, we anticipate that the 3D placement engine will be able to manage the # 3D nets, the overall HPWL, and the vertical interconnects better.

6.4 Proposed Approach: Five Tiers and Above

Suppose we have an ARD constructed for two, three, and four tiers. For more than four tiers, we can construct 3D routing topologies using the ARD as follows (considering a five-tier case):

First, we begin the routing topology construction by projecting all the pins in the tiers above Tier 3 onto Tier 3. Now, all the pins are located in four tiers, so we can use the ARD to find all MMRSMTs for the (projected) pin locations. Then, we move the projected pins back to their original tiers. When we expand them, we insert vertical edges to connect the projected pins and the MMRSMTs. Of course, we can project the pins in many different ways (e.g., project the pins in the tiers below Tier 1 onto Tier 1), which will help generate many different routing topologies.

One of the problems of this methodology is that it does not use planar wires in the tiers above Tier 3, which might cause routing congestion in Tier 0 through Tier 3. We can solve this problem in many different ways like the following: