ABSTRACT
The Boolean satisfiability problem (SAT), an NP-complete problem, poses significant challenges for conventional general-purpose computers due to its inherent “combinatorial explosion” nature. Fast SAT solvers, however, offer immense potential for smart city applications, such as optimal planning and scheduling in logistics and communication, driving the need for innovative solving methods. Implementing a high-speed SAT solver on a field programmable gate array (FPGA) by exploiting its variable-level parallelism and energy efficiency is a promising approach for applications requiring time-critical control and low energy consumption at the network edge. Inspired by the deformation behavior of an amoeboid organism, the "AmoebaSAT" algorithm has emerged as a novel solution search process for the SAT problem, enabling the parallel updating of all state variables. Although state-of-the-art studies on FPGA-implemented AmoebaSATs have successfully addressed smaller 3-SAT instances with several hundred variables, they adopt an instance-specific approach, requiring pre-processing or synthesizing the FPGA configuration each time the targeted SAT instance changes. This study introduces a modified algorithm, “AmoebaSATone,” incorporating a novel feedback control mechanism alongside the original bounceback control for more efficient resource utilization. The authors implement AmoebaSATone on a Zynq FPGA board, employing an instance-general approach that targets arbitrary instances without regenerating configuration data, while facilitating easy algorithm setting updates. FPGA-implemented AmoebaSATone effectively solves large 3-SAT instances with problem sizes up to 120,000 variables (523,200 clauses), previously unattainable on a single FPGA board. Compared to a CPU implementation on a Ryzen server, the FPGA-AmoebaSATone achieved a speedup ranging from 3.2 to 14.8 times. These results showcase the potential of the AmoebaSATone algorithm for solving SAT-based problems on a larger scale, paving the way for further research on dedicated edge-oriented problem-solving hardware.
- Masashi Aono. 2020. Amoeba-inspired combinatorial optimization machines. Japanese Journal of Applied Physics 59, 6 (2020), 060502. https://doi.org/10.35848/1347-4065/ab8e05 arXiv:http://jjap.jsap.jp/link?JJAP/59/060502/Google ScholarCross Ref
- Masashi Aono, Makoto Naruse, Song-Ju Kim, Masamitsu Wakabayashi, Hirokazu Hori, Motoichi Ohtsu, and Masahiko Hara. 2013. Amoeba-inspired nanoarchitectonic computing: solving intractable computational problems using nanoscale photoexcitation transfer dynamics. Langmuir 29, 24 (2013), 7557–7564.Google ScholarCross Ref
- Maliheh Aramon, Gili Rosenberg, Elisabetta Valiante, Toshiyuki Miyazawa, Hirotaka Tamura, and Helmut G Katzgraber. 2019. Physics-inspired optimization for quadratic unconstrained problems using a digital annealer. Frontiers in Physics 7 (2019), 48.Google ScholarCross Ref
- Armin Biere, Marijn Heule, and Hans van Maaren. 2009. Handbook of satisfiability. Vol. 185. IOS press.Google Scholar
- S. A. Cook. 1971. The complexity of theorem-proving procedures. In Proceedings of the 3rd Annual ACM Symposium on Theory of Computing (STOC’71). ACM, 151–158.Google ScholarDigital Library
- M. R. Garey and D. S. Johnson. 1979. Computers and Intractability: A Guide to the Theory of NP-Completeness. W.H. Freeman and Company, New York.Google ScholarDigital Library
- Hayato Goto, Kotaro Endo, Masaru Suzuki, Yoshisato Sakai, Taro Kanao, Yohei Hamakawa, Ryo Hidaka, Masaya Yamasaki, and Kosuke Tatsumura. 2021. High-performance combinatorial optimization based on classical mechanics. Science Advances 7, 6 (2021), eabe7953.Google Scholar
- K. Hara, N.Takeuchi, and M. Aono. 2019. Amoeba-inspired stochastic hardware SAT solver. In International Symposium on Quality Electronic Design.Google Scholar
- Takahiro Inagaki, Yoshitaka Haribara, Koji Igarashi, Tomohiro Sonobe, Shuhei Tamate, Toshimori Honjo, Alireza Marandi, Peter L McMahon, Takeshi Umeki, Koji Enbutsu, 2016. A coherent Ising machine for 2000-node optimization problems. Science 354, 6312 (2016), 603–606.Google Scholar
- Takumi Inage, Kazuei Hironaka, Kensuke Iizuka, Kohei Ito, Yasuyu Fukushima, Mitaro Namiki, and Hideharu Amano. 2021. M-KUBOS/PYNQ Cluster for multi-access edge computing. In 2021 Ninth International Symposium on Computing and Networking (CANDAR). 95–101. https://doi.org/10.1109/CANDAR53791.2021.00020Google ScholarCross Ref
- Mark W Johnson, Mohammad HS Amin, Suzanne Gildert, Trevor Lanting, Firas Hamze, Neil Dickson, Richard Harris, Andrew J Berkley, Jan Johansson, Paul Bunyk, 2011. Quantum annealing with manufactured spins. Nature 473, 7346 (2011), 194–198.Google Scholar
- K. Kanazawa and T. Maruyama. 2010. An Approach for Solving Large SAT Problems on FPGA. In ACM Transactions on Reconfigurable Technology and Systems, Vol. 4.Google Scholar
- K. Kanazawa and T. Maruyama. 2014. An Approach for solving SAT/Max-SAT solving using variable-way cache. In 24th Int. Conf. FPL.Google Scholar
- M.Aono. 2020. Claiming the benefit of priority from Japanese Patent Application. P2020-184993.Google Scholar
- Naeimeh Mohseni, Peter L. McMahon, and Tim Byrnes. 2022. Ising machines as hardware solvers of combinatorial optimization problems. Nature Reviews Physics 4, 6 (2022), 363–379. https://doi.org/10.1038/s42254-022-00440-8Google ScholarCross Ref
- Yu Nakayama, Yuko Hara-Azumi, Anh Hoang Ngoc Nguyen, Daisuke Hisano, Yoshiaki Inoue, Takayuki Nishio, and Kazuki Maruta. 2020. Real-Time Routing for Wireless Relay Fronthaul with Vehicle-Mounted Radio Units. In 2020 IEEE 91st Vehicular Technology Conference (VTC2020-Spring). IEEE, 1–6.Google Scholar
- Yu Nakayama, Ryo Yaegashi, Anh Hoang Ngoc Nguyen, and Yuko Hara-Azumi. 2021. Real-Time Reconfiguration of Time-Aware Shaper for ULL Transmission in Dynamic Conditions. IEEE Access 9 (2021), 115246–115255. https://doi.org/10.1109/ACCESS.2021.3105420Google ScholarCross Ref
- A. H. N. Nguyen, M. Aono, and Y. Hara-Azumi. 2019. Amoeba-inspired hardware sat solver with effective feedback control. In 2019 International Conference on Field-Programmable Technology (ICFPT). IEEE, 243–246.Google Scholar
- A. H. N. Nguyen, M. Aono, and Y. Hara-Azumi. 2020. FPGA-Based Hardware/Software Co-Design of a Bio-Inspired SAT Solver. IEEE Access 8 (2020), 49053–49065.Google ScholarCross Ref
- Anh Hoang Ngoc Nguyen and Yuko Hara-Azumi. 2021. An FPGA-based Stochastic SAT Solver Leveraging Inter-Variable Dependencies. In 2021 31st International Conference on Field-Programmable Logic and Applications (FPL). 179–184. https://doi.org/10.1109/FPL53798.2021.00037Google ScholarCross Ref
- PALTEK. 2023. FPGA computing platform MKUBOS. https://www.paltek.co.jp/design/original/m/-kubos/. https://www.paltek.co.jp/design/original/m/-kubos/Google Scholar
- SATLIB. 2023. SATLIB benchmark Problems. SATLIB. https://www.cs.ubc.ca// hoos/SATLIB/benchm.htmlGoogle Scholar
- Ali Asgar Sohanghpurwala, Mohamed W Hassan, and Peter Athanas. 2017. Hardware accelerated SAT solvers: a survey. J. Parallel and Distrib. Comput. 106 (2017), 170–184.Google ScholarCross Ref
- P. Surynek, A. Felner, R. Stern, and E. Boyarski. 2016. Efficient SAT approach to multi-agent path finding under the sum of costs objective. In Proceedings of the Twenty-second European Conference on Artificial Intelligence. 810–818.Google Scholar
- P. Surynek, A. Felner, R. Stern, and E. Boyarski. 2018. Sub-optimal SAT-based approach to multi-agent path-finding problem. In Proceedings of the 11th Annual Symposium on Combinatorial Search (SoCS 2018). 90–105.Google Scholar
- Takashi Takemoto, Kasho Yamamoto, Chihiro Yoshimura, Masato Hayashi, Masafumi Tada, Hiroaki Saito, Mayumi Mashimo, and Masanao Yamaoka. 2021. 4.6 A 144Kb Annealing System Composed of 9x16Kb Annealing Processor Chips with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems. In 2021 IEEE International Solid- State Circuits Conference (ISSCC), Vol. 64. 64–66. https://doi.org/10.1109/ISSCC42613.2021.9365748Google ScholarCross Ref
- N. Takeuchi, M.Aono, and N. Yoshikawa. 2019. Superconductor amoeba-inspired SAT solvers for combinatorial optimization. In Physical Review Applied, Vol. 11.Google Scholar
- Ying Jie Yan, Hideharu Amano, Masashi Aono, Kaori Ohkoda, Shingo Fukuda, Kenta Saito, and Seiya Kasai. 2021. Resource-saving FPGA Implementation of the Satisfiability Problem Solver: AmoebaSATslim. In 2021 International Conference on Field-Programmable Technology (ICFPT). 1–5. https://doi.org/10.1109/ICFPT52863.2021.9609882Google ScholarCross Ref
Index Terms
- Efficient FPGA Implementation of Amoeba-inspired SAT Solver with Feedback and Bounceback Control: Harnessing Variable-Level Parallelism for Large-Scale Problem Solving in Edge Computing
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