Wenju He
ABSTRACT
Here we present the design and implementation of our LLVM-based Ahead-Of-Time (AOT) SYCL CPU device without using SPIR-V, known as non-SPIRV CPU device. Our design of non-SPIRV CPU device is intended to highlight a general SYCL CPU implementation that aims for both debuggability and performance. Contributions:
• Streamline compiler optimization pipeline by integrating kernel optimizations and transformations into LLVM C++ pipeline.
• Eliminate SPIR-V IR generation during the CPU device code compilation and leverage LLVM IR from compiler front-end directly to reduce compilation overhead and preserve IR information including debug info, among LLVM passes.
- Xinmin Tian, Hideki Saito, Ernesto Su, Jin Lin, Satish Guggilla, Diego Caballero, Matt Masten 2017. LLVM compiler implementation for explicit parallelization and SIMD vectorization. In Proceedings of the Fourth Workshop on the LLVM Compiler Infrastructure in HPC, pp. 1-11. 2017. DOI: https://doi.org/10.1145/3148173.3148191Google Scholar
Digital Library
- Matt Masten, Evgeniy Tyurin, Konstantina Mitropoulou, Eric Garcia, and Hideki Saito. 2018. Function/kernel vectorization via loop vectorizer. In 2018 IEEE/ACM 5th Workshop on the LLVM Compiler Infrastructure in HPC (LLVM-HPC), pp. 39-48. IEEE, 2018. DOI: https://doi.org/10.1109/LLVM-HPC.2018.8639483Google ScholarCross Ref
- Jin, Zheming. The rodinia benchmark suite in SYCL. No. ANL/ALCF-20/06. Argonne National Lab.(ANL), Argonne, IL (United States). Argonne Leadership Computing Facility (ALCF), 2020.Google Scholar
Index Terms
- Streamline Ahead-of-Time SYCL CPU Device Implementation through Bypassing SPIR-V
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