ABSTRACT
Quality of a true 3D placement approach greatly relies on the correctness of the models used in its formulation. However, the models used by previous approaches are not precise enough. Moreover, they do not actually place TSVs which makes their approach unable to get accurate wirelength and construct a correct congestion map. Besides, they rarely discuss routability which is the most important issue considered in 2D placement. To resolve this insufficiency, this paper proposes more accurate models to estimate placement utilization and TSV number by the softmax function which can align cells to exact tiers. Moreover, we propose a fast parallel algorithm to update the locations of TSVs when cells are moved during optimization. Finally, we present a novel penalty model to estimate routing overflow of regions covered by cells and inflate cells in congested regions according to this model. Experimental results show that our methodology can obtain better results than previous works.
- P. Batude et al., "Advances in 3D CMOS sequential integration." in Proc. IEEE IEDM, pp. 1--4, Dec 2009.Google Scholar
- P. Batude et al., "Demonstration of low temperature 3D sequential FDSOI integration down to 50 nm gate length," 2011 Symposium on VLSI Technology - Digest of Technical Papers, pp. 158--159, 2011.Google Scholar
- T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Yao-Wen Chang, "NTUplace3: an analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints," IEEE TCAD, vol. 27, no. 7, pp. 1228--1240, July 2008.Google ScholarDigital Library
- C. Cheng, A. B. Kahng, I. Kang, and L. Wang, "RePlAce: advancing solution quality and routability validation in global placement," IEEE TCAD, vol. 38, no. 9, pp. 1717--1730, Sept. 2019.Google Scholar
- J. Cong and G. Luo, "A multilevel analytical placement for 3D ICs," in Proc. ASP-DAC, pp. 361--366, Feb. 2009.Google Scholar
- J. Cong and G. Luo. "An analytical placer for mixed-size 3D placement," in Proc. of ISPD, pp. 61--66, March 2010.Google Scholar
- B. Goplen and S. Sapatnekar, "Placement of 3D ICs with thermal and interlayer via considerations," in Proc. of DAC, pp. 626--631, June 2007.Google Scholar
- X. He, Y. Wang, Y. Guo, and E. F. Y. Young, "Ripple 2.0: improved movement of cells in routability-driven placement," IEEE TCAD, vol. 22, no. 10, pp. 1--26, Dec. 2016.Google Scholar
- M. Hsu, V. Balabanov and Y. Chang, "TSV-aware analytical placement for 3-D IC designs based on a novel weighted-average wirelength model," IEEE TCAD, vol. 32, no. 4, pp. 497--509, April 2013.Google ScholarDigital Library
- M.-K. Hsu, Y.-F. Chen, C.-C. Huang, S. Chou, T.-H. Lin, T.-C. Chen, and Y.-W. Chang, "NTUplace4h: a novel routability-driven placement algorithm for hierarchical mixed-size circuit designs," IEEE TCAD, vol. 33, no. 12, pp. 1914--1927, Dec. 2014.Google ScholarCross Ref
- C.-C. Huang, H.-Y. Lee, B.-Q. Lin, S.-W. Yang, C.-H. Chang, S.-T. Chen, and Y.-W. Chang, "NTUplace4dr: a detailed-routing-driven placer for mixed-size circuit designs with technology and region constraints," IEEE TCAD, vol. 37, no. 3, pp. 669--681, March 2018.Google ScholarCross Ref
- Z.-W. Jiang, B.-Y. Su, and Y.-W. Chang, "Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs," in Proc. of DAC, pp. 167--172, July 2008.Google Scholar
- A.B. Kahng and Q. Wang, "Implementation and extensibility of an analytic placer" IEEE TCAD, vol. 24, no. 5, pp. 734--747, May 2005.Google Scholar
- G. Karypis and V. Kumar, "hMETIS, a hypergraph partitioning package version 1.5.3," http://glaros.dtc.umn.edu/gkhome/metis/hmetis/downloadGoogle Scholar
- M.-C. Kim, J. Hu, D. J. Lee, and I. L. Markov, "A SimPLR method for routability driven placement," in Proc. of ICCAD, pp. 67--73, Dec. 2011.Google Scholar
- T. Lin and C. Chu, "POLAR 2.0: an effective routability-driven placer," in Proc. of DAC, pp. 1--6, Aug. 2014.Google Scholar
- J.-M. Lin, S.-T. Li and Y.-T. Wang, "Routability-driven mixed-size placement prototyping approach considering design hierarchy and indirect connectivity between macros," in Proc. of DAC, pp. 1--6, Aug. 2019.Google Scholar
- J.-M. Lin, Y.-L. Deng, Y.-C. Yang, J.-J. Chen and Y.-C. Chen, "A Novel Macro Placement Approach based on Simulated Evolution Algorithm," in Proc. of ICCAD, pp. 1--7, 2019.Google Scholar
- J.-M. Lin, Y.-L. Deng, Y.-C. Yang, and J.-J. Chen, P.-C. Lu, "Dataflow-aware Macro Placement based on Simulated Evolution Algorithm for Mixed-Size Designs," IEEE TVLSI, Vol. 29, No. 5, Oct. 2021.Google Scholar
- J. Lu et al., "ePlace-3D: electrostatics based placement for 3D-ICs," in Proc. of ISPD, pp. 11--18, April 2016.Google Scholar
- T. Lu, Z. Yang and A. Srivastava, "Electromigration-aware placement for 3D-ICs" in Proc. of ISQED, pp. 35--40, May 2016.Google Scholar
- G. Luo, Y. Shi and J. Cong, "An analytical placement framework for 3-D ICs and its extension on thermal awareness," IEEE TCAD, vol. 32, no. 4, pp. 510--523, April 2013.Google Scholar
- Heechun Park, Bon Woong Ku, Kyungwook Chang, Da Eun Shim, and Sung Kyu Lim. "Pseudo-3D approaches for commercial-grade RTL-to-GDS tool flow targeting monolithic 3D ICs," in Proc. of ISPD, pp. 47--54, March 2020.Google Scholar
- N. Sillon, A. Astier, H. Boutry, L. Di Cioccio, D. Henry and P. Leduc, "Enabling technologies for 3D integration: From packaging miniaturization to advanced stacked ICs," IEEE IEDM, pp. 1--4, Dec. 2008.Google Scholar
- P. Spindler and F. M. Johannes, "Fast and accurate routing demand estimation for efficient routability-driven placement," in Proc. of DATE, pp. 1--6, May 2007.Google Scholar
- Synopsys. IC Compiler. https://www.synopsys.com.Google Scholar
- S. S. Wong and A. E. Gamal, "The prospect of 3D-IC," in Proc. of CICC, pp. 445--448, Sep. 2009.Google Scholar
- Himax Technologies, Inc. https://www.himax.com.tw/zh/company/about-himax/Google Scholar
Index Terms
- Routability-Driven Analytical Placement with Precise Penalty Models for Large-Scale 3D ICs
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