CpU: practical components for systems software

The HaL PM1 CPU is the first implementation of the 64-bit SPARC Version 9 instruction set architecture. The processor utilizes superscalar instruction issue, register renaming, and a dataflow model of execution. Instructions can complete out-of-order ...

The PA-8000 RISC CPU is the first implementation of a new generation of microprocessors from Hewlett-Packard Company. The processor was designed for high-end systems and to support the new 64-bit PA-RISC 2.0 architecture. The aggressive four-way ...

TIS is an instruction-level methodology for processor core self-testing that enhances instruction set of a CPU with test instructions. Since the functionality of test instructions is the same as the NOP instruction, NOP instructions can be replaced with ...