Thomas Ferrère
ABSTRACT
Safety and security are major concerns in the development of Cyber-Physical Systems (CPS). Signal temporal logic (STL) was proposed as a language to specify and monitor the correctness of CPS relative to formalized requirements. Incorporating STL into a development process enables designers to automatically monitor and diagnose traces, compute robustness estimates based on requirements, and perform requirement falsification, leading to productivity gains in verification and validation activities; however, in its current form STL is agnostic to the input/output classification of signals, and this negatively impacts the relevance of the analysis results.
In this paper we propose to make the interface explicit in the STL language by introducing input/output signal declarations. We then define new measures of input vacuity and output robustness that better reflect the nature of the system and the specification intent. The resulting framework, which we call interface-aware signal temporal logic (IA-STL), aids verification and validation activities. We demonstrate the benefits of IA-STL on several CPS analysis activities: (1) robustness-driven sensitivity analysis, (2) falsification and (3) fault localization. We describe an implementation of our enhancement to STL and associated notions of robustness and vacuity in a prototype extension of Breach, a MATLAB®/Simulink® toolbox for CPS verification and validation. We explore these methodological improvements and evaluate our results on two examples from the automotive domain: a benchmark powertrain control system and a hydrogen fuel cell system.
- J. Kapinski, J. V. Deshmukh, X. Jin, H. Ito, and K. Butts, "Simulation-based approaches for verification of embedded control systems: An overview of traditional and advanced modeling, testing, and verification techniques," IEEE Control Systems Magazine, vol. 36, no. 6, pp. 45--64, Dec 2016.Google Scholar
Cross Ref
- O. Maler and D. Nickovic, "Monitoring temporal properties of continuous signals," in Formal Techniques, Modelling and Analysis of Timed and Fault-Tolerant Systems (FORMATS/FTRTFT), 2004, pp. 152--166.Google Scholar
- G. E. Fainekos and G.J. Pappas, "Robustness of temporal logic specifications," in Formal Approaches to Software Testing and Runtime Verification, First Combined International Workshops, FATES 2006 and RV 2006, Seattle, WA, USA, August 15--16, 2006, Revised Selected Papers, 2006, pp. 178--192. Google ScholarDigital Library
- G. E. Fainekos and G.J. Pappas, "Robustness of temporal logic specifications for continuous-time signals," Theor. Comput. Sci., vol. 410, no. 42, pp. 4262--4291, 2009. Google ScholarDigital Library
- A. Donzé and O. Maler, "Robust satisfaction of temporal logic over real-valued signals," in Formal Modeling and Analysis of Timed Systems (FORMATS), 2010, pp. 92--106. Google ScholarDigital Library
- A. Donzé, T. Ferrère, and O. Maler, "Efficient robust monitoring for STL," in International Conference on Computer Aided Verification. Springer, 2013, pp. 264--279.Google Scholar
- A. Donzé, "Breach, A toolbox for verification and parameter synthesis of hybrid systems," in Computer Aided Verification, 22nd International Conference, CAV 2010, Edinburgh, UK, July 15--19, 2010. Proceedings, 2010, pp. 167--170. Google ScholarDigital Library
- Y. Annpureddy, C. Liu, G. E. Fainekos, and S. Sankaranarayanan, "S-taliro: A tool for temporal logic falsification for hybrid systems," in Tools and Algorithms for the Construction and Analysis of Systems (TACAS), 2011, pp. 254--257. Google ScholarDigital Library
- E. Plaku, L. E. Kavraki, and M. Y. Vardi, "Falsification of LTL safety properties in hybrid systems," in International Conference on Tools and Algorithms for the Construction and Analysis of Systems. Springer, 2009, pp. 368--382. Google ScholarDigital Library
- T. Nghiem, S. Sankaranarayanan, G. Fainekos, F. Ivancié, A. Gupta, and G. J. Pappas, "Monte-carlo techniques for falsification of temporal properties of nonlinear hybrid systems," in Proceedings of the 13th ACM international conference on Hybrid systems: computation and control. ACM, 2010, pp. 211--220. Google ScholarDigital Library
- W. Li, A. Forin, and S. A. Seshia, "Scalable specification mining for verification and diagnosis," in Proceedings of the 47th design automation conference. ACM, 2010, pp. 755--760. Google ScholarDigital Library
- E. Bartocci, L. Bortolussi, and G. Sanguinetti, "Data-driven statistical learning of temporal logic properties," in Formal Modeling and Analysis of Timed Systems (FORMATS), 2014, pp. 23--37.Google Scholar
- Z. Kong, A. Jones, and C. Belta, "Temporal logics for learning and detection of anomalous behavior," IEEE Trans. Automat. Contr., vol. 62, no. 3, pp. 1210--1222, 2017.Google ScholarCross Ref
- E. Asarin, A. Donzé, O. Maler, and D. Nickovic, "Parametric identification of temporal properties," in Runtime Verification, 2011, pp. 147--160. Google ScholarDigital Library
- H. Yang, B. Hoxha, and G. Fainekos, "Querying parametric temporal logic properties on embedded systems," in IFIP International Conference on Testing Software and Systems. Springer, 2012, pp. 136--151.Google Scholar
- X. Jin, A. Donzé, J. V. Deshmukh, and S. A. Seshia, "Mining requirements from closed-loop control models," IEEE Trans. on CAD of Integrated Circuits and Systems, vol. 34, no. 11, pp. 1704--1717, 2015.Google ScholarDigital Library
- A. Bakhirkin, T. Ferrère, and O. Maler, "Efficient parametric identification for STL," in Proceedings of the 21st International Conference on Hybrid Systems: Computation and Control (part of CPS Week). ACM, 2018, pp. 177--186. Google ScholarDigital Library
- A. Benveniste, B. Caillaud, D. Nickovic, R. Passerone, J. Raclet, P. Reinkemeier, A. L. Sangiovanni-Vincentelli, W. Damm, T. A. Henzinger, and K. G. Larsen, "Contracts for system design," Foundations and Trends in Electronic Design Automation, vol. 12, no. 2--3, pp. 124--400, 2018.Google Scholar
- E. Bartocci, T. Ferrère, N. Manjunath, and D. Nickovic, "Localizing faults in simulink/stateflow models with STL," in Proceedings of the 21st International Conference on Hybrid Systems: Computation and Control (part of CPS Week), HSCC 2018, Porto, Portugal, April 11--13, 2018, 2018, pp. 197--206. Google ScholarDigital Library
- J. Kapinski, X. Jin, J. Deshmukh, A. Donze, T. Yamaguchi, H. Ito, T. Kaga, S. Kobuna, and S. Seshia, "ST-Lib: A library for specifying and classifying model behaviors," SAE Technical Paper, Tech. Rep., 2016.Google Scholar
- T. Akazaki, "Falsification of conditional safety properties for cyber-physical systems with gaussian process regression," in Runtime Verification - 16th International Conference, RV, 2016, pp. 439--446.Google Scholar
- A. Dokhanchi, S. Yaghoubi, B. Hoxha, and G. Fainekos, "Vacuity aware falsification for MTL request-response specifications," in 2017 13th IEEE Conference on Automation Science and Engineering (CASE), Aug 2017, pp. 1332--1337.Google Scholar
- I. Beer, S. Ben-David, C. Eisner, and Y. Rodeh, "Efficient detection of vacuity in ACTL formulaas," in Computer Aided Verification, 9th International Conference, CAV, 1997, pp. 279--290. Google ScholarDigital Library
- O. Kupferman and M. Y. Vardi, "Vacuity detection in temporal model checking," in Correct Hardware Design and Verification Methods (CHARME), 1999, pp. 82--96. Google ScholarDigital Library
- T. Ball and O. Kupferman, "Vacuity in testing," in Tests and Proofs, Second International Conference, TAP, 2008, pp. 4--17. Google ScholarDigital Library
- T. Ferrère, O. Maler, and D. Nickovic, "Trace diagnostics using temporal implicants," in Automated Technology for Verification and Analysis, 2015, pp. 241--258.Google ScholarCross Ref
- X. Jin, J. V. Deshmukh, J. Kapinski, K. Ueda, and K. Butts, "Powertrain Control Verification Benchmark," in Proc. of Hybrid Systems: Computation and Control, 2014, pp. 253--262 Google ScholarDigital Library
- A. Adimoolam, T. Dang, A. Donzé, J. Kapinski, and X. Jin, "Classification and coverage-based falsification for embedded control systems," in Computer Aided Verification, R. Majumdar and V. Kunčak, Eds. Cham: Springer International Publishing, 2017, pp. 483--503.Google Scholar
Index Terms
- Interface-aware signal temporal logic
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