Josep Rius
- [1] J. Galiay, Y. Crouzet, M. Vergniault, "Physical versus Logic fault Models in MOS LSI Circuits: Impact on their Testability", IEEE Trans. on Computers, June 1980, pp. 527-531.Google Scholar
Digital Library
- [2] M. Levi, "CMOS is Most Testable", Proc. of ITC, 1981, pp. 217-220.Google Scholar
- [3] Y.K. Malaiya, S.Y.H. Su, "A New Fault Model and Testing Techniques for CMOS Devices", Proc. of ITC, 1982, pp. 25-34.Google Scholar
- [4] J.M. Soden, C.F. Hawkins, R.K. Gulati, W. Mao, "IDDQ Testing: A Review", JETTA, December 1992, pp. 291-304.Google Scholar
- [5] K.J. Lee, M.A. Breuer, "Design and Test Rules for CMOS Circuits to Facilitate IDDQ Testing of Bridging Faults", IEEE Trans. on CAD, May 1992, pp. 659- 670.Google ScholarDigital Library
- [6] M.A. Ortega, J. Rius, J. Figueras, "Test of CMOS Circuits based on their Energy Consumption", IDDQ'96, October 1996, pp. 36-40. Google ScholarDigital Library
- [7] W. Nebel, J.P. Mermet, "Low Power Design in deep Submicron Electronics", KLUWER, December 1997. Google ScholarDigital Library
- [8] NEC Corporation. "μPD78014 User's manual", 1993Google Scholar
- [9] M. Keating, D. Meyer, "A New Approach to Dynamic IDD Testing", Proc. of ITC'87, pp. 316-319, 1987.Google Scholar
- [10] B. Vinnakota, W. Jiang, D. Sun, "Process-Tolerant Test with the Energy Consumption Ratio", Proc. of ITC'98, pp. 1027-1036, October 1998. Google ScholarDigital Library
- [11] S.T. Su, R.Z. Makki, T. Nagle, "Transient Power Supply Current Monitoring- A New Test Method for CMOS VLSI Circuits", JETTA, 6:23-43, February, 1995. Google ScholarDigital Library
- [12] J. A. Segura, M. aoca, D. Mateo, A. Rubio, "An Approach to Dynamic Power Consumption Current Testing of CMOS ICs",. Proceedings of VTS'95, pp. 95- 100, April 1995. Google ScholarDigital Library
Index Terms
- Exploring the combination of IDDQ and iDDt testing: energy testing
Recommendations
IDDT Testing versus IDDQ Testing
IDDQ testing has progressed to become a worldwide accepted test method to detect CMOS IC defects. However, it is noticed that observing the average transient current can lead to improvements in real defect coverage, which is referred to IDDT testing. This ...
Deep Sub-Micron IDDQ Testing: Issues and Solutions
EDTC '97: Proceedings of the 1997 European conference on Design and TestThe effectiveness of I/sub DDQ/ testing in deep sub-micron is threatened by the increased transistor sub-threshold leakage current. In this article, we survey possible solutions and propose a deep sub-micron I/sub DDQ/ test mode. The methodology ...
IDDQ Testing: Issues Present and Future
IDDQ testing has emerged from a company-specific CMOS IC test technology in the 1960's and 1970's to a worldwide-accepted technique that is a requirement for low-defect PPM levels and failure rates. It is the single most sensitive test method to detect ...
Comments