Zhen Zhang
ABSTRACT
A 10 Gb/s continuous-time linear adaptive equalizer IC for 10 Gigabit short-reach optical interconnects using GLOBALFOUNDRIES (GF) 0.13 μm SiGe BiCMOS technology is described. The circuit consists of a continuous-time linear equalizer, an adaptation loop using spectrum balancing technique, an on-chip bandgap reference (BGR), and a low-dropout regulator (LDO). The adaptation loop is designed to minimize the inter-symbol interference (ISI) according to the variety of the characteristics of front-end devices. The BGR and LDO are designed and optimized to improve the power supply noise rejection (PSNR). The whole chip occupies an area of 900 μm × 850 μm and dissipates 106 mW from a 3.3 V power supply. The adaptive equalizer has a boosting factor up to 19 dB at 5 GHz and the PSNR is better than 35 dB over the frequency range up to 10 MHz.
- Rylyakov, A. et al. 2012. Transmitter Predistortion for Simultaneous Improvements in Bit Rate, Sensitivity, Jitter, and Power Efficiency in 20 Gb/s CMOS-Driven VCSEL Links. J. Lightwave Technol.. 30, 4 (2012), 399--405.Google Scholar
Cross Ref
- Choi, J. et al. 2004. A 0.18-μm CMOS 3.5-Gb/s Continuous-Time Adaptive Cable Equalizer Using Enhanced Low-Frequency Gain Control Method. IEEE J. Solid-State Circuits. 39, 3 (2004), 419--425.Google ScholarCross Ref
- El-Gammal, K. A. et al. 2015. A 10 Gbps ADC-Based Equalizer for Serial I/O Receiver. In Proceedings of the 10th International Design & Test Symposium (IDT), 38--43.Google Scholar
- Kim, Y. et al. 2016. A 21-Gbit/s 1.63-pJ/bit Adaptive CTLE and One-Tap DFE with Single Loop Spectrum Balancing Method. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24, 2 (2016), 789--793.Google ScholarCross Ref
- Kocaman, N. et al. 2016. A 3.8 mW/Gbps Quad-Channel 8.5-13 Gbps Serial Link with a 5 Tap DFE and a 4 Tap Transmit FFE in 28 nm CMOS. IEEE J. Solid-State Circuits. 51, 4 (2016), 881--892.Google ScholarCross Ref
- Beyene, W. T. 2008. The Design of Continuous-Time Linear Equalizers Using Model Order Reduction Techniques. 2008 IEEE-EPEP Electrical Performance of Electronic Packaging, 187--190.Google Scholar
- Guangyu Evelina Zhang, and Green, M. 2005. A 10 Gb/s BiCMOS Adaptive Cable Equalizer. IEEE J. Solid-State Circuits. 40, 11 (2005), 2132--2140.Google ScholarCross Ref
- Lee, D. et al. 2010. An 8.5-Gb/s Fully Integrated CMOS Optoelectronic Receiver Using Slope-Detection Adaptive Equalizer. IEEE J. Solid-State Circuits. 45, 12 (2010), 2861--2873.Google ScholarCross Ref
- Lee, J. 2006. A 20-Gb/s Adaptive Equalizer in 0.13-μm CMOS Technology. IEEE J. Solid-State Circuits. 41, 9 (2006), 2058--2066.Google ScholarCross Ref
- Sun, R. 2005. A Low-Power 20-Gb/s Continuous-Time Adaptive Passive Equalizer. Carnegie Institute of Technology of the Carnegie Mellon University.Google Scholar
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