Tse-Yu Yeh
- 1.T-Y Yeh and Y.N. Putt, "Two-Level Adaptive Branch Prediction", Technical Report CSE-TR-I17-91, Com. puter Science and Engineering Division, Department o} EECS, The University of Michigan, (Nov. 1991).Google Scholar
Digital Library
- 2.T-Y Yeh and Y.N. Part, "Two-Level Adaptive Branch Prediction", The g$th A CM/IEEE International Symposium and Workshop on Microarchitecture, (Nov. 1991), pp. 51-61. Google ScholarDigital Library
- 3.M. Butler, T-Y Yeh, Y.N. Patt, M. Alsup, {{. Scales, and M. Shebanow, "Instruction Level Parallelism is Greater Than Two", Proceedings of the 18th International Sympossum on Computer Architecture, (May. 1991), pp. 276-286. Google ScholarDigital Library
- 4.D. R. Kaefi and P. G. Emma, "Branch History Table Prediction of Moving Target Branches Due to Subroutine Returns" , Proceedings o} the 18th international Symposium on Computer Architecture, (May 1991), pp. 34--42. Google ScholarDigital Library
- 5.Motorola Inc., "M88100 User's ManuaJ', Phoenix, Arizona, (March 13, 1989).Google Scholar
- 6.W.W. Hwu, T.M.Conte, and P.P.Chang, "Comparing Software and Hardware Schemes for Reducing the Cost of Branches", Proceedings of the 16th International Symposium on Computer Architecture, (May 1989). Google ScholarDigital Library
- 7.N.P. Jouppi and D. Wall, "Available Instruction-Level Parallelism for Superscalar and Superpipelined Machines.", Proceedings of the Third International Con. ference on Architectural Support for Programming Languages and Operating Systems, (April 1989), pp. 272- 282. Google ScholarDigital Library
- 8.D. J. Lilja, "Reducing the Branch Penalty in Pipelined Processors ", IEEE Computer, (July 1988), pp.47-55. Google ScholarDigital Library
- 9.W.W. Hwu and Y.N. Part, "Checkpoint Repair for Out-of-order Execution Machines", IEEE Transactions on Computers, (December 1987), pp.1496-1514. Google ScholarDigital Library
- 10.P. G. Emma and E. S. Davidson, "Characterization of Branch and Data Dependencies in Programs for Evaluating Pipeline Performance" , IEEE Transactions on Computers, (July 1987), pp.859-876. Google ScholarDigital Library
- 11.J. A. DeRma and H. M. Levy, "An Evaluation of Branch Architectures ", Proceedings o/the 1~th Inter. national Symposium on Computer Architecture, (June 1987), pp.10-16. Google ScholarDigital Library
- 12.D.R. Ditzel and H.R. McLellaaa, "Branch Folding in the CRISP Microprocessor: Reducing Branch Delay to Zeron, Proceedings of the 14th International Symposium on Computer Architecture, (June 1987), pp.2-9. Google ScholarDigital Library
- 13.S. McFarling and J. Hennessy, "Reducing the Coat of Branches", Proceedings of the 13th international Symposium on Computer Architecture, (1986), pp.396-403. Google ScholarDigital Library
- 14.J. Lee and A. J. Smith, "Branch Prediction Strategies and Branch Target Buffer Design", IEEE Computer, (January 1984), pp.6-22.Google ScholarDigital Library
- 15.T.R. Gross and J. Hennessy, "Optimizing Delayed Branches", Proceedings of the 15th Annual Workshop on Microprogramming, (Oct. 1982), pp.114-120. Google ScholarDigital Library
- 16.D.A. Patterson and C.H. Sequin, "RISC-I: A Reduced Instruction Set VLSI Computer", Proceedings of the 8th International Symposium on Computer Architecture, (May. 1981), pp.443-458. Google ScholarDigital Library
- 17.J.E. Smith, "A Study of Branch Prediction Strategies", Proceedings of the 8th International Symposium on Computer Architecture, (May. 1981), pp.135-148. Google ScholarDigital Library
- 18.T. C. Chen, "Parallelism, Pipelining and Computer Efficiency", Computer Design, Vol. 10, No. 1, (Jan. 1971), pp.69-74.Google Scholar
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- Alternative implementations of two-level adaptive branch prediction
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Alternative implementations of two-level adaptive branch prediction
Special Issue: Proceedings of the 19th annual international symposium on Computer architecture (ISCA '92)As the issue rate and depth of pipelining of high performance Superscalar processors increase, the importance of an excellent branch predictor becomes more vital to delivering the potential performance of a wide-issue, deep pipelined microarchitecture. ...
Alternative implementations of two-level adaptive branch prediction
ISCA '92: Proceedings of the 19th annual international symposium on Computer architectureAs the issue rate and depth of pipelining of high performance Superscalar processors increase, the importance of an excellent branch predictor becomes more vital to delivering the potential performance of a wide-issue, deep pipelined microarchitecture. ...
Applying Caching to Two-Level Adaptive Branch Prediction
DSD '01: Proceedings of the Euromicro Symposium on Digital Systems DesignAbstract: During the 1990s Two-level Adaptive Branch Predictors were developed to meet the requirement for accurate branch prediction in high-performance superscalar processors. However, while two-level adaptive predictors achieve very high prediction ...
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