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Setting an error detection infrastructure with low cost acoustic wave detectors

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Published:09 June 2012Publication History
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Abstract

The continuing decrease in dimensions and operating voltage of transistors has increased their sensitivity against radiation phenomena making soft errors an important challenge in future chip multiprocessors (CMPs). Hence, new techniques for detecting errors in the logic and memories that allow meeting the desired failures-in-time (FIT) budget in CMPs are required.

This paper proposes a low-cost dynamic particle strike detection mechanism through acoustic wave detectors. Our results show that our mechanism can protect both the logic and the memory arrays. As a case study, we also show how this technique can be combined with error codes to protect the last-level cache at low cost.

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      • Published in

        cover image ACM SIGARCH Computer Architecture News
        ACM SIGARCH Computer Architecture News  Volume 40, Issue 3
        ISCA '12
        June 2012
        559 pages
        ISSN:0163-5964
        DOI:10.1145/2366231
        Issue’s Table of Contents
        • cover image ACM Conferences
          ISCA '12: Proceedings of the 39th Annual International Symposium on Computer Architecture
          June 2012
          584 pages
          ISBN:9781450316422

        Copyright © 2012 ACM

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        • Published: 9 June 2012

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