Kimon Karras
ABSTRACT
Ethernet, although initially conceived as a Local Area Network technology, has been steadily making inroads into access and core networks. This has led to a need for higher link speeds, which are now reaching 100 Gbit/s. Packet processing at this rate represents a significant challenge, that needs to be met efficiently, while minimizing power consumption and chip area. This level of throughput favours a pipelined approach, thus this paper takes a traditional pipeline and breaks it down to mini-pipelines, which can perform coarse-grained processing (like process an MPLS label to completion). These mini-pipelines are then parellelized and used to construct a folded pipeline architecture, which augments the traditional approach by significantly reducing power consumption, a key problem in future routers. The paper compares the two approaches, discusses their advantages and disadvantages and demonstrates by quantitative measures that the folded pipeline architecture is the better solution for 100 Gbit/s processing.
- Ieee standard for local and metropolitan area networks---virtual bridged local area networks - amendment: Provider backbone bridge traffic engineering.Google Scholar
- Netronome nfp-3200 network processor - http://www.netronome.com/files/file/netronome0).pdf.Google Scholar
- Xelerated AB. Hx network processor family, http://www.xelerated.com.Google Scholar
- S. Blake, D. Black, M. Carlson, E. Davies, Z. Wang, and W. Weiss. Rfc2475 - an architecture for differentiated services, December 1998.Google Scholar
- M. Bocci, S. Bryant, and L. Levrau. A framework for mpls in transport networks, November 2008.Google Scholar
- M. Bocci, M. Vigoureux, and S. Bryant. Rfc5586 - mpls generic associated channel, June 2009.Google Scholar
- A. Broder and M. Mitzenmacher. Using multiple hash functions to improve ip lookups. In INFOCOM 2001. Twentieth Annual Joint Conference of the IEEE Computer and Communications Societies. Proceedings. IEEE, volume 3, pages 1454--1463 vol. 3, 2001.Google ScholarCross Ref
- EZ Chip. Np-4 network processor family, http://www.ezchip.com.Google Scholar
- D. Fedyk and D. Allan. Ethernet data plane evolution for provider networks. IEEE Communications Magazine, 46:84--89, 2008. Google ScholarDigital Library
- S. Hauger, A. Mutter, A. Kirstaedter, T. Wild, K. Karras, R. Ohlendorf, F. Feller, and J. Scharf. Packet processing at 100 gbps and beyond - challenges and perspectives. In 10. ITG-Fachtagung Photonische Netze, 2009.Google Scholar
- CSwitch Inc. Cs90 configurable switch array family, http:/www.cswitch.com.Google Scholar
- A. Kirstadter, C. Gruber, J. Riedl, and T. Bauschert. Carrier-grade ethernet for packet core networks. volume 6354, page 635414. SPIE, 2006.Google Scholar
- Ian Kuon and Jonathan Rose. Measuring the gap between fpgas and asics. In FPGA '06: Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays, pages 21--30, New York, NY, USA, 2006. ACM. Google ScholarDigital Library
- B. Niven-Jenkins, D. Brungard, M. Betts, N. Sprecher, and S. Ueno. Mpls-tp requirements, April 2009.Google Scholar
- Mohammad Peyravian and Jean Calvignac. Fundamental architectural considerations for network processors. Comput. Netw., 41(5):587--600, 2003. Google ScholarDigital Library
- E. Rosen, A. Viswanathan, and R. Callon. Rfc3031 - multiprotocol label switching architecture, January 2001.Google Scholar
- Haoyu Song, Sarang Dharmapurikar, Jonathan Turner, and John Lockwood. Fast hash table lookup using extended bloom filter: an aid to network processing. In SIGCOMM '05: Proceedings of the 2005 conference on Applications, technologies, architectures, and protocols for computer communications, pages 181--192, New York, NY, USA, 2005. ACM. Google ScholarDigital Library
- Ning Weng and Tilman Wolf. Pipelining vs. multiprocessors - choosing the right network processor system topology. In in Proc. of Advanced Networking and Communications Hardware Workshop (ANCHOR 2004) in conjunction with The 31st Annual International Symposium on Computer Architecture (ISCA 2004, 2004.Google Scholar
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