ABSTRACT
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction level. To have an accurate timing behavior, we had to firstly solve timing issues in processor modeling, secondly define fast and precise cache models, and thirdly solve the synchronization issues due to the different models of computation used in the ISSes and in the rest of the system. We present an integration solution that covers these issues and detail its implementation. We have experimented our proposal using processors models provided by the QEMU framework to replace the existing ISSes and SystemC TLM as simulation environment for the whole platform. This approach proposes a range of solutions trading off simulation speed versus accuracy. The experiments show that even for the most precise configuration, the simulation speedup is still significant.
- Soclib project. http://soclib.lip6.fr.Google Scholar
- D. August, J. Chang, S.Girbal, D. G. Perez, G. Mouchard, D. Penry, O. Temam, and N. Vachharajani. Unisim: An open simulation environment and library for complex architecture design and collaborative development. IEEE Computer Architecture Letters (CAL'07), 2007. Google ScholarDigital Library
- V. Bala, E. Duesterwald, and S. Banerjia. Dynamo: a transparent dynamic optimization system. In Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation, pages 1--12, Vancouver, British Columbia, Canada, 2000. Google ScholarDigital Library
- P. Barham, B. Dragovic, K. Fraser, S. Hand, T. Harris, A. Ho, R. Neugebauer, I. Pratt, and A. Warfield. Xen and the art of virtualization. In Proceedings of the nineteenth ACM symposium on Operating systems principles, pages 164--177, Bolton Landing, NY, USA, 2003. Google ScholarDigital Library
- F. Bellard. Qemu, a fast and portable dynamic translator. In Proceedings of the USENIX Annual Technical Conference, pages 41--46, Anaheim, CA, 2005. USENIX Association. Google ScholarDigital Library
- V. Berman. Standards: The P1685 IP-XACT IP Metadata Standard. Design&Test of Computers, IEEE, 23(4):316--317, Apr. 2006. Google ScholarDigital Library
- R. Buchmann, F. Pétrot, and A. Greiner. Fast cycle accurate simulator to simulate event-driven behavior. In Proceedings of the International Conference on Electrical, Electronic and Computer Engineering, pages 35--38, 2004.Google ScholarCross Ref
- L. Cai and D. Gajski. Transaction level modeling: an overview. pages 19--24, Oct 2003.Google Scholar
- C. Cifuentes and V. Malhotra. Binary translation: Static, dynamic, retargetable? Software Maintenance, IEEE International Conference on, 0:340, 1996. Google ScholarDigital Library
- R. J. Creasy. The origin of the VM/370 time-sharing system. IBM Journal of Research&Development, 25(5):483--490, 1981.Google ScholarDigital Library
- G. De Micheli, R. Ernst, and W. Wolf, editors. Readings in hardware/software co-design. Kluwer Academic Publishers, 2002. Google ScholarDigital Library
- F. Devaux. Mechanisms for cpu virtualization, 2005. International patent number WO/2006/027488.Google Scholar
- S. Devine, E. Buignon, and M. Rosenblum. Virtualization system including a virtual machine monitor for computer with segmented architecture, Oct. 1998. US patent number 6397242.Google Scholar
- P. Gerin, X. Guérin, and F. Pétrot. Efficient implementation of native software simulation for mpsoc. In DATE '08: Proceedings of the conference on Design, automation and test in Europe, pages 676--681, Munich, Germany, 2008. Google ScholarDigital Library
- F. Ghenassia, editor. Transaction Level Modeling With SystemC: TLM Concepts And Applications for Embedded Systems. Springer Verlag, 2006. Google ScholarDigital Library
- G. R. Hellestrand, R. L. K. Chan, M. C. Kam, and J. R. Torossian. Hardware and software co-simulation including executing an analyzed user program, Oct. 1999. patent nb : 6230114.Google Scholar
- A. A. Jerraya, A. Bouchhima, and F. Pétrot. Programming models and hw-sw interfaces abstraction for multi-processor soc. In Proceedings of the 43rd annual conference on Design automation, pages 280--285, 2006. Google ScholarDigital Library
- M. Monton, A. Portero, M. Moreno, B. Martinez, and J. Carrabina. Mixed sw/systemc soc emulation framework. In Industrial Electronics, 2007. ISIE 2007. IEEE International Symposium on, pages 2338--2341, 2007.Google ScholarCross Ref
- F. Pétrot and P. Gomez. Lightweight implementation of the posix threads api for an on-chip mips multiprocessor with vci interconnect. In Proceedings of the conference Design Automation and Test in Europe, pages 20051--20056, mar 2003. Google ScholarDigital Library
- K. Popovici, X. Guerin, F. Rousseau, P. S. Paolucci, and A. A. Jerraya. Platform-based software design flow for heterogeneous mpsoc. ACM Trans. Embed. Comput. Syst., 7(4):1--23, 2008. Google ScholarDigital Library
- L. Scheffer, L. Lavagno, and G. Martin, editors. EDA for IC System Design, Verification, and Testing. CRC Taylor&Francis, 1 edition, March 2006. Section II, System Level Design. Google ScholarDigital Library
- J. Schnerr, O. Bringmann, and W. Rosenstiel. Cycle accurate binary translation for simulation acceleration in rapid prototyping of socs. In DATE '05: Proceedings of the conference on Design, Automation and Test in Europe, pages 792--797, Washington, DC, USA, 2005. IEEE Computer Society. Google ScholarDigital Library
- R. L. Sites, A. Chernoff, M. B. Kirk, M. P. Marks, and S. G. Robinson. Binary translation. Commun. ACM, 36(2):69--81, 1993. Google ScholarDigital Library
- SystemC available online at http://www.systemc.org/.Google Scholar
- P. van der Wolf, E. de Kock, T. Henriksson, W. Kruijtzer, and G. Essink. Design and programming of embedded multiprocessors: an interface centric approach. pages 206--217, Sept. 2004.Google Scholar
- V. Zivojnovic and H. Meyr. Compiled hw/sw co-simulation. In Proceedings of the 33rd annual conference on Design automation, pages 690--695, Las Vegas, Nevada, United States, 1996. Google ScholarDigital Library
Index Terms
- Using binary translation in event driven simulation for fast and flexible MPSoC simulation
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