Steven Jay Meyer
Abstract
In my view this year's Physical Design Conference brought forth a number of interesting open questions. The questions involve the following three areas: active area utilization in semicustom circuits, comparison of standard cell and gate array area efficiency, and problems associated with multiple wiring layers.
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Digital Library
- Burstein, M., Hong S. J., and Nair, R. Spatial distribution of wires in master-slice VLSI. Proceedings IEEE International Conference on Circuits and Computers, 1982, 265--269.Google Scholar
- Heller, W. R., Hsi, C. G., and Mikhail, W. F. Wirability--designing wiring space for chips and chip packages, IEEE Design & Test (August 1984), 43--50.Google Scholar
- Meyer, S. J. A constructive placement algorithm for logic arrays. Proceedings IEEE ICCD '83, 1983, 58--61.Google Scholar
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