Shiho Hagiwara
ABSTRACT
Stochastic approaches for effective power supply network optimization are proposed. Considering node voltages obtained using dynamic voltage drop analysis as sample variables, multi-variate regression is conducted to optimize clock timing metrics, such as clock skew or jitter. Aggregate correlation coefficient (ACC) which quantifies the resistivity between different chip regions is defined in order to find apossible insufficiency in the wire connections of the powersupply network. Based on the ACC, we also propose a procedure using linear regression to find the most effective region for improving clock timing metrics. In our example, clockskew has been reduced by 20% through two iterations.
- A. Chandrakasan, W. J. Bowhill, and F. Fox. Design of high-performance microprocessor circuits, chapter 12. IEEE press, 2001. Google Scholar
Digital Library
- T. Enami, M. Hashimoto, and T. Onoye. Statistical modeling technique of power-supply voltage variation by principal component analysis. IPSJ Symposium series, 2006(7):205--210, 2006. (in Japanese).Google Scholar
- D. Harris and S. Naffziger. Statistical clock skew modeling with data delay variations. IEEE Trans. VLSI, 9(6):888--898, Dec. 2001. Google ScholarDigital Library
- M. Hashimoto, J. Yamaguchi, T. Sato, and H. Onodera. Timing analysis considering temporal supply voltage fluctuation. In Proc. ASP-DAC, pages 1098--1101, 2005. Google ScholarDigital Library
- M. Hashimoto, T. Yamamoto, and H. Onodera. Statistical analysis of clock skew variation in H-tree structure. In Proc. ISQED, pages 402--407, March 2005. Google ScholarDigital Library
- Y. Liu, S. R. Nassif, L. T. Pileggi, and A. J. Strojwas. Impact of interconnect variations on the clock skew of a gigahertz microprocessor. In Proc. DAC, pages 168--171, 2000. Google ScholarDigital Library
- R. Saleh, S. Hussain, S. Rochel, and D. Overhauser. Clock skew verification in the presence of IR-drop in the power distribution network. IEEE trans. CAD, 19(6):635--644, June 2000. Google ScholarDigital Library
- K. T. Tang and E. G. Friedman. Estimation of transient voltage fluctuations in the CMOS-based power distribution networks. In Proc. ISCAS, pages 463--466, 2001.Google ScholarCross Ref
Index Terms
- Improvement of power distribution network using correlation-based regression analysis
Recommendations
Application of Correlation-Based Regression Analysis for Improvement of Power Distribution Network
Stochastic approaches for effective power distribution network optimization are proposed. Considering node voltages obtained using dynamic voltage drop analysis as sample variables, multi-variate regression is conducted to optimize clock timing metrics, ...
Influence of distributed power supply in distributed power distribution network
Ethical Computational Intelligence for Cyber MarketIn distribution networks with distributed power supplies, distributed power supplies can also be used as backup power sources to support the grid. If a distribution network contains multiple distributed power sources, the distribution network becomes a ...
Low-power clock distribution using multiple voltages and reduced swings
Clock networks account for a significant fraction of the power dissipation of a chip and are critical to performance. This paper presents theory and algorithms for building a low-power clock tree by distributing the clock signal at a lower voltage and ...
Comments