- AlGo90 G.S. Almasi and A. Gottlieb, Highly Parallel Computing, Benjamin/Cummings Publishing Co. Inc., pp. 425-429, 1990. Google ScholarDigital Library
- CRAY82 CRAY-1 Computers, Hardware Reference Manual, Chippewa Fails, WI, Cray Research Inc., 1982.Google Scholar
- HwBr84 K. Hwang and F. Briggs, Computer Architecture and Parallel Processing, McGraw-Hill Book Co., pp. 669-684, 1984. Google ScholarDigital Library
- JoWa89 N. P. Jouppi and D. W. Wall "Available Instruction-Level Parallelism for Superscalar and Superpipelined Machines," Third International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 272-282 April 1989. Google ScholarDigital Library
- KaDa79 W. J. Kaminsky and E. S. Davidson, "Developing a Multiple-instruction-Stream Single-Chip Processor," Computer, pp. 66-76, December 1979.Google Scholar
- McMa84 F. H. McMahon, "LLNL FORTRAN KER- NELS: MFLOPS," Lawrence Livermore Laboratories, Livermore, CA, March 1984.Google Scholar
- PaSm83 N. Pang and J. E. Smith, CRAY-1 Simulation Tools, Tech. Report ECE-83-11, University of Wisconsin-Madison, Dec. 1983.Google Scholar
- PlSo88 "The Performance Potential of Multiple Functional Unit Processors," Proceedings of the 15th Annual Symposium on Computer Architecture, pp. 37-44, June 1985. Google ScholarDigital Library
- Russ78 R.M. Russel, "The CRAY-1 Computer System," Communications of the ACM, vol. 21, no. 1, pp. 63-72, January 1978. Google ScholarDigital Library
- Smit81 B.J. Smith, "Architecture and Applications of the HEP Multiprocessor Computer System," SPIE Real Time Signal Processing IV, Vol. 298, pp. 241-248, Aug. 1981.Google ScholarCross Ref
- Thor70 J.E. Thornton, Design of a Computer - The Control Data 6600, Scott, Foresman and Co,. 1970. Google ScholarDigital Library
Index Terms
- Strategies for achieving improved processor throughput
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