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Lithography faces today many challenges to meet the ITRS road-map. 193nm is still today the only existing
industrial option to address high volume production for the 22nm node. Nevertheless to achieve such a resolution, double
exposure is mandatory for critical level patterning. EUV lithography is still challenged by the availability of high power
source and mask defectivity and suffers from a high cost of ownership perspective. Its introduction is now not foreseen
before 2015.
Parallel to these mask-based technologies, maskless lithography regularly makes significant progress in terms of
potential and maturity. The massively parallel e-beam solution appears as a real candidate for high volume
manufacturing. Several industrial projects are under development, one in the US, with the KLA REBL project and two in
Europe driven by IMS Nanofabrication (Austria) and MAPPER (The Netherlands).
Among the developments to be performed to secure the takeoff of the multi-beam technology, the availability of a
rapid and robust data treatment solution will be one of the major challenges. Within this data preparation flow, advanced
proximity effect corrections must be implemented to address the 16nm node and below. This paper will detail this
process and compare correction strategies in terms of robustness and accuracy. It will be based on results obtained using
a MAPPER tool within the IMAGINE program driven by CEA-LETI, in Grenoble, France. All proximity effects
corrections and the dithering step were performed using the software platform Inscale® from Aselta Nanographics. One
important advantage of Inscale® is the ability to combine both model based dose and geometry adjustment to accurately
pattern critical features. The paper will focus on the advantage of combining those two corrections at the 16nm node
instead of using only geometry corrections. Thanks to the simulation capability of Inscale®, pattern fidelity and
correction robustness will be evaluated and compared between the correction strategies. This work will be lead on the
most critical layers of the 16nm integrate circuits layouts which are contact and metal 1. Finally the aim of this paper is
to demonstrate that a complete data preparation flow including advanced proximity effects corrections, simulation and
verification capabilities is available for the maskless lithography at the 16nm node and below, through the direct write
version of Inscale®. This data preparation platform is already in use in several laboratories for direct write processes.
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