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This paper discusses an unusual series of problems encountered in etching the poly 1 floating gates of an EEPROM device. Such devices feature two levels of polysilicon: a control gate composed of poly 2, and a 'floating gate' which consists of lightly doped poly 1. The failure modes originates as a result of the highly anisotropic nature of floating gate etch recipe, as well as the unusual implant doping scheme used with this particular device. We experienced a significant yield problem involving the definition of the floating gate which resulted in localized 'pitting' of the silicon adjacent to the floating gate structure. This pitting occurred as a result of an unusual behavior mode sometimes exhibited by etchant ions, and it caused the poly 2 control gate to short to the substrate. This short resulted in a byte failure. The initial solution to this problem eliminated the pitting, but introduce dan unintended degeneration of the side-wall profile of the poly 1 floating gate. This new failure modality generated bit failures. This paper presents a detailed description of both failure mechanisms and the sophisticated four-step etch recipe used to eliminate them. As the importance of non-volatile memory to the semiconductor industry increases, these failure modes will become more commonplace, and the solutions presented here of increasing value.
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