VHDL implementation of an image processor

Michael Kelly; Kenneth W. Hsu

doi:10.1117/12.311078

18 June 1998 VHDL implementation of an image processor

Michael Kelly, Kenneth W. Hsu

Proceedings Volume 3422, Input/Output and Imaging Technologies; (1998) https://doi.org/10.1117/12.311078
Event: Asia Pacific Symposium on Optoelectronics '98, 1998, Taipei, Taiwan

Abstract

This paper describes the design of a flexible, pipelined general image processor (GIP) using VHDL to model the top level design and functional blocks consisting of histogram [1,2,3,4,5,6], modification, convolution, halftone, error diffusion, and threshold. GIP was simulated to have a processing speed of 70 Mpixels/second. A four pixel wide image data path is used so a clock of 17.5 MHz can be used. Mentor Graphics tool suites were used to perform the simulation and synthesis of the design. The total number of gates in 1.2 (mu) CMOSN gate array was estimated to be 236 K gates, less than 1 million transistors.

Citation Download Citation

Michael Kelly and Kenneth W. Hsu "VHDL implementation of an image processor", Proc. SPIE 3422, Input/Output and Imaging Technologies, (18 June 1998); https://doi.org/10.1117/12.311078

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KEYWORDS

Image processing

Clocks

Convolution

Halftones

Image filtering

Linear filtering

Diffusion

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