FIFO design based on verilog HDL

Changyu Chen

doi:10.1117/12.2672696

28 March 2023 FIFO design based on verilog HDL

Changyu Chen

Proceedings Volume 12597, Second International Conference on Statistics, Applied Mathematics, and Computing Science (CSAMCS 2022); 125972S (2023) https://doi.org/10.1117/12.2672696
Event: Second International Conference on Statistics, Applied Mathematics, and Computing Science (CSAMCS 2022), 2022, Nanjing, China

Abstract

Asynchronous FIFO (Frist Input Frist Output) is one of the most effective methods for solving the sub-stability caused by data transmission and storage across clock domains. Asynchronous FIFO has a wide range of applications in areas such as radar, signal processing and multimedia technology. A wide range of applications. This paper firstly introduces the Verilog HDL language and the characteristics of synchronous FIFOs and asynchronous FIFOs to solve the metastable problem as a starting point, using asynchronous FIFO design, which is one of the effective methods to solve the metastable state. This paper analyses two difficult points in FIFO design: how to generate empty-full flags and reduce the probability of metastable errors. A new design approach is adopted: using a grey code counter and a secondary D flip-flop can effectively solve the metastable problem by generating the empty/full status bits through the grey code pointer to accomplish the above difficult points. Simulation results show that the data in the asynchronous FIFO can be written and read out normally, and the null/full flag signal is correct. The design of asynchronous FIFO can greatly reduce the probability of sub-stability and make the product more stable and efficient.

Citation Download Citation

Changyu Chen "FIFO design based on verilog HDL", Proc. SPIE 12597, Second International Conference on Statistics, Applied Mathematics, and Computing Science (CSAMCS 2022), 125972S (28 March 2023); https://doi.org/10.1117/12.2672696

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KEYWORDS

Clocks

Design and modelling

Binary data

Data storage

Logic

Data transmission

Error analysis

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