1 Introduction

Ferroelectric field-effect transistors (FeFETs) have the potential to achieve super-steep subthreshold swing (SS) or high driving currents suitable for ultra-low power consumption due to Fe dielectric layer induced negative capacitance and a high dielectric constant [1,2,3,4]. The most readily available Si complementary metal oxide semiconductor (CMOS)-compatible field-effect (FE) material is HfxZr1-xO2 (HZO), which has robust ferroelectricity and can be formed into thin films (< 20 nm), which may benefit scaling down of CMOS [5,6,7].

Recently, experimental evidence of performance enhancement and typical FE-induced characteristics, e.g., negative drain induced barrier lowering (N-DIBL), negative differential resistance (NDR), sub-60 mV·dec−1 of SSs, and improved on-state current have been reported for devices with thick HZO layers [8,9,10,11,12,13]. However, most typical characteristics are not obvious in advanced technology node logic devices based on ultra-thin HZO films in gate stacks, due to the weak ferroelectricity of thinner films. This effect has obstructed further exploration of super steep SS technology applied to advanced technology nodes [14,15,16,17,18]. Furthermore, although many experimental devices with HZO dielectrics have been reported, circuits based on FeFETs have rarely been demonstrated, and may yield improved performances on a circuit level [19,20,21].

In this work, ferroelectric fin field-effect transistors (Fe FinFETs) and circuits using the main-stream “gate-last process” were fabricated with integration of a 3 nm ultra-thin HZO layer into the gate stacks. The enhanced ferroelectricity of the 3 nm HZO film caused by Al doping from the TiAlC capping layer contributed to obvious performance improvements in Fe FinFETs-based CMOS devices and circuits.

2 Experimental

The process flow that was used to fabricate FinFET devices and circuits with HZO and HfO2 is illustrated in Fig. 1a. This basic process is similar to that used for developing n- and p-type devices on separate wafers [22, 23]. The FinFETs featuring a replacement metal gate were developed on the 200-mm Si (100) wafers. Initially, a self-aligned spacer image transfer technique was employed to pattern the fin morphology. Subsequently, standard procedures for punch-through stop doping (PTSD) and fin shallow trench isolation (STI) were adopted. Dummy gates constructed from amorphous silicon were fabricated using direct-write electron beam and dry etching techniques. After procedures for dummy gate planarization and removal had been carried out, atomic layer deposition (ALD) was applied to produce dual-work-function metal gates, which were used to set the threshold voltages (VT) of the n- and p-type FETs after fabrication of the interfacial layer (IL) and high-k dielectric layer. The diagrams in Fig. 1b demonstrate the intricate layered films of the n- and p-type devices. The uniform 3 nm thick HZO and HfO2 dielectric layers were produced through alternate incorporation of organic precursors based on Hf or Zr. The device contact processes for the source and drain (SD) W-plug and gate were applied to form the contact holes. Forming gas annealing (FGA) at 450 °C for 30 min was applied to the Al electrode of both devices with HZO crystallization.

Fig. 1
figure 1

a Fabrication process of FinFETs with a FE film replacing metal gate; b detailed gate stack layers of n- and p-type FET; c schematic diagram, d TEM image and e EDX mapping images of a p-FinFET with 3-nm HZO

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Transmission electron microscope (TEM) imaging was used to examine the cross-sectional profiles of FinFETs. The electrical characterization was conducted using semiconductor parameter analyzers Keithley 4200 and Agilent 4156 C.

3 Results and discussion

3.1 Ferroelectricity enhancement of 3 nm HZO film

Figure 1c–e shows a schematic diagram, TEM images (cut across AA′), and energy dispersive X-ray spectroscopy (EDX) mappings of HZO-based FinFETs, respectively. Figure 1d shows that the fin had a top thickness of 4 nm and a height of approximately 70 nm. The interfacial layer (IL) and HZO layers were 1 and 3 nm thick, respectively, which gave superior gate control over the channel. Figure 1e shows the elements distribution of a p-type device, revealing the conformal work function metal layers around the entire 3D fins channel. Hf and Zr atoms concentrated in the medium layer, but Al diffused into the adjacent layers.

To verify the elemental diffusion, the distribution of the elements in the devices is shown in Fig. 2a. Elemental line scans (along BB′ in Fig. 1d) indicate obvious diffusion of Al into the TiN layer to form Al-doped TiN due to the strong diffuse tendency of Al atoms (especially considering the annealing process at 450 °C).

Fig. 2
figure 2

a Corresponding line scan for N, Al, Ti and Zr, respectively; b PUND results of current signals of HZO-based capacitor with Al-doped TiN; c comparison of Pr from capacitors with HZO/Al-TiN, HZO/TiN, and HfO/TiN; d XRD patterns of samples with and without Al-doped TiN; e schematic diagram of interactions between HZO films and Al-doped TiN and TiN capping layers

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Figure 2b shows positive-up-negative-down (PUND) results measured using a voltage pulse (1 V, 50 μs) on an HZO-based capacitor with a similar structure to the gate stacks of the HZO-based FinFETs. The polarization switching current (Ips) and the non-switching current (Ins), which was measured during the application of the second voltage pulse, constitute the transient current (Is) arising from the application of the first voltage pulse [24]. By integrating the Ips signal, which is the difference between Is and Ins, the remnant polarization values are obtained. Accordingly, a comparison of the capacitances based on 3 nm HZO with Al-doped TiN and TiN electrodes is identified, as shown in Fig. 2c. Compared with the capacitance of the device with a TiN electrode, an improvement in the Pr value of approximately 20% was obtained with the Al-doped TiN electrode. Figure 2d shows XRD patterns of the 3 nm HZO films with Al-doped TiN and TiN capping layers. The orthorhombic phase was confirmed in both films. Furthermore, consistent with the PUND results, for the Al-doped TiN capping layers, the (111) peak was sharp and intense, indicating good crystallinity and chemical ordering [25,26,27]. This result is mainly attributed to the presence of AlOx at the interface that may facilitate HZO film crystallization, as shown in Fig. 2e, and has also been reported for other elemental oxides [28,29,30].

3.1.1 HZO-based devices results

The electrical characteristics of the FinFETs with 3-nm HfO and HZO were subsequently investigated. Figure 3a, c shows the transfer curves of both types of CMOS FinFETs at VDS of |100| mV (LIN) and |800| mV (SAT), respectively. Unlike the devices based on HfO2 as the dielectric layer, an obvious N-DIBL phenomenon was observed for the FinFET with 3-nm HZO due to its enhanced ferroelectricity. Importantly, owing to the N-DIBL effect, the IDS in the subthreshold region of the HZO-based devices was much larger than that of the FinFETs with HfO2.

Fig. 3
figure 3

a IDS-VGS curves of p-type HZO-based FinFET at various VDS; b extracted VT as a function of IDS of device in a; c IDS-VGS curves of n-type HZO-based FinFET at various VDS; d extracted VT as a function of IDS of device in c; measured IDS-VDS curves and NDR phenomenon of e n-type and f p-type FinFETs with 3-nm HZO; g, h extracted GDS as a function of VDS under various VGS for p- and n-type HZO-based FinFETs in e, f

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To investigate the N-DIBL effects further, dual-sweep IDS-VGS curves were obtained over a range of VDS, and the extracted VT values for p- and n-type HZO-based FinFETs at various VDS biases are shown in Fig. 3b, d, respectively. The values of the VT@FOR and VT@REV decreased (increased) as VDS steadily increased for p-type (n-type) HZO-based FinFET, indicating the presence of the N-DIBL over almost the whole VDS range. In addition, the hysteresis (defined as VT@FOR − VT@REV) was negligible and very stable. Specifically, the hysteresis was stable at ~ 90 and ~ 110 mV for the n- and p-type HZO-based FinFETs with different VDS, respectively, which was much smaller than values of previously reported devices [21]. Furthermore, a clear negative differential resistance (NDR) stemming from the N-DIBL effect was also observed in the output curves of HZO-based CMOS devices (Fig. 3e, f for n- and p-type devices, respectively). In addition, the NDR phenomenon became more obvious at higher VGS, which was consistent with the conclusions of previous theoretical predictions [9, 10]. The extracted differential resistance, defined as GDS, as a function of VDS curves is illustrated in Fig. 3g, h, indicating that HZO-FinFETs with 3 nm ultra-thin HZO have a negative GDS. Specifically, for the p-type HZO-FinFET shown in Fig. 3g, when VGS is less than − 0.5 V, a low negative GDS occurs. As VGS increases to − 0.6 V, partial GDS values change from positive to negative. Notably, unlike the smooth GDS–VDS curves previously reported [9, 10], the GDS values appeared to fluctuate around 0 at higher VGS, which might indicate that the NC effect in this work was dynamic rather than static as previously reported [31–32]. Figure 3h shows that as VGS increases to 0.9 V, the partial GDS values also change from positive to negative in n-type devices which is consistent with the behavior of a p-type transistor.

Figure 4a shows the distribution of DIBLs for the HZO-based and HfO-based FinFETs over 60 devices. There are few N-DIBL characteristics for FinFETs based on conventional HfO2 films. However, The N-DIBL phenomenon was observed for almost all HZO-based FinFETs, indicating good uniformity and stability of the devices. The median values of DIBLs were − 0.003 and 0.012 V for HZO- and HfO2-FinFET devices, respectively. In addition to N-DIBL and NDR, the ferroelectric effect was also reflected in the improved SS, as shown in Fig. 4b. Although the SSs of FinFETs with a 3 nm ultra-thin HZO layer did not exceed the limit of 60 mV·dec−1, the subthreshold voltage switching characteristics of HfO2-based FinFETs were improved compared with those of the HfO2-FinFETs. The SS distribution in Fig. 4b indicates that the median SS was approximately 67.5 mV·dec−1 for the HZO-based FinFETs and 79.7 for the HfO2-based FinFETs mV·dec−1. Therefore, a decrease in the average SS of ∼12.2 mV·dec−1 was achieved for the Fe FinFETs.

Fig. 4
figure 4

a Distribution of DIBL values of HZO-based FinFETs and HfO2-based FinFETs; b distribution of SS values of HZO-based FinFET and control FinFET; c Ion-Ioff mappings for HZO-based FinFET and HfO2-based FinFET at VDS = 0.8 V; d Ion-Ioff mappings for HZO-based FinFET and HfO2-based FinFET at VDS = 0.4 V

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Figure 4c, d shows ION-IOFF distributions of HZO- and HfO2-based FinFETs at 0.8 and 0.4 V VDD, respectively. The performance of the two types of devices was almost the same when VDD = 0.8 V. However, when VDS was decreased to 0.4 V, the off-current of the HZO-based FinFET decreased by an order of magnitude compared to that of the FinFET with a 3-nm HZO at the same level of on-current. This result is attributed to the obvious FE effects.

3.1.2 HZO-based FinFET circuits results

Figure 5a shows typical voltage transfer curves (VTC) of HZO- and HfO-based FinFETs CMOS inverters in a series of supply voltages. The maximum voltage gain of the two CMOS inverters exhibited little difference under high supply voltages. However, the voltage gain of the HZO-based FinFET inverter was greater than that of the controlled inverter when the supply voltage was lower than 0.6 V, which might have been caused by the higher IDS at lower VDDs due to N-DIBL phenomenon (Fig. 5b). These characteristics indicate the potential for the application of these devices in low-power integrated circuits. Additionally, Fig. 5d shows the output waveforms of 55-stage ring oscillators (ROs, Fig. 5c) for the HZO- and HfO-based FinFETs. The oscillation frequencies of the HfO-based and HZO-based FinFETs were 178 and 222 kHz, respectively. Owing to the performance of the HZO-based FinFETs, a 19.9% increase in oscillation frequency and a 16% reduction in delay per stage were achieved for the HZO-based FinFET circuits compared with those of circuits based on FinFET with 3 nm HZOs.

Fig. 5
figure 5

a Voltage transfer curve of inverters based on FinFET with 3-nm HZO and HfO; b voltage gain of HZO-based-CMOS and HfO-based CMOS inverters; c optical images of ROs; d output waveforms of HfO-based FinFET and HZO-based FinFET 55-stage ring oscillators

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4 Conclusion

The ferroelectricity of ultra-thin 3-nm Hf0.5Zr0.5O2 film is increased by our proposed approach that involves the use of an Al-doped TiN electrode. The CMOS HZO-based FinFETs with Al-doped stacks show clear N-DIBL and NDR characteristics. Furthermore, the IDS values of HZO-based FinFETs were improved compared with those of a FinFET with 3 nm HfO2. Enhanced performance (i.e., higher gain of inverters at low VDD) was also confirmed in circuits based on HZO-based FinFETs, demonstrating the feasibility of these devices in ultra-low power applications.