Design and Economic Considerations to Achieve the Price Parity of SiC MOSFETs with Silicon IGBTs
p.889
p.889
Readiness of SiC MOSFETs for Aerospace and Industrial Applications
p.894
p.894
Experimental and Theoretical Study of 4H-SiC JFET Threshold Voltage Body Bias Effect from 25 °C to 500 °C
p.903
p.903
Processing and Prolonged 500 °C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect
p.908
p.908
Modelling of 4H-SiC VJFETs with Self-Aligned Contacts
p.913
p.913
Conduction Loss Reduction for Bipolar Injection Field-Effect-Transistors (BIFET)
p.917
p.917
A 500 °C Monolithic SiC BJT Latched Comparator
p.921
p.921
Design Impact on the Static and Short-Circuit Characteristics of SiC-SIT with Non-Uniformly Doped Channel
p.925
p.925
Current Gain Stability of SiC Junction Transistors Subjected to Long-Duration DC and Pulsed Current Stress
p.929
p.929
Modelling of 4H-SiC VJFETs with Self-Aligned Contacts
Abstract:
Purely vertical 4H-SiC JFETs have been modeled by using three different approaches: the analytical model, the finite element model and the compact model. The results of the modeling have been compared with experimental results on a series of fabricated self-aligned devices with two different channel lengths (0.3 and 1.1μm) and various channel widths (1.5, 2, 2.5, 3, 4 and 5 μm). For all the considered models I-V and C-V characteristics could be satisfactorily simulated.
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Info:
Periodical:
Materials Science Forum (Volume 858)
Pages:
913-916
Citation:
Online since:
May 2016
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