Deepashree Sengupta
Sachin S. Sapatnekar
ABSTRACT
A wide variety of error tolerant applications supports the use of approximate circuits that achieve power savings by introducing small errors. This paper proposes a fast and novel algorithm for the design of such circuits with the goal of maximizing power savings, constrained by a fixed error budget, through an analytical expression to optimally select the number of bits to be approximated. This algorithm outperforms uniform approximation schemes by over 30% in power savings, with negligible computational overhead.
- J. Han and M. Orshansky, "Approximate Computing: An Emerging Paradigm For Energy-Efficient Design," in Proc. ETS, pp. 1--6, 2013.Google Scholar
Cross Ref
- M. Shafique, et al., "Invited - Cross-layer Approximate Computing: From Logic to Architectures," in Proc. DAC, pp. 99:1--99:6, 2016. Google ScholarDigital Library
- J. Huang, et al., "A Methodology for Energy-Quality Tradeoff Using Imprecise Hardware," in Proc. DAC, pp. 504--509, 2012. Google ScholarDigital Library
- E. Swartzlander, "Truncated Multiplication with Approximate Rounding," in Proc. 33rd Asilomar Conf. Signals, Systems, Computers, vol. 2, pp. 1480--1483, 1999.Google Scholar
- V. Gupta, et al., "Low-Power Digital Signal Processing Using Approximate Adders," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 32, no. 1, pp. 124--137, 2013. Google ScholarDigital Library
- J. M. Jou, et al., "Design of Low-error Fixed-width Multipliers for DSP Applications," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 46, no. 6, pp. 836--842, 1999.Google ScholarCross Ref
- L. Chen, et al., "Design of Approximate Unsigned Integer Non-restoring Divider for Inexact Computing," in Proc. GLSVLSI, pp. 51--56, 2015. Google ScholarDigital Library
- F. S. Snigdha, et al., "Optimal Design of JPEG Hardware Under the Approximate Computing Paradigm," in Proc. DAC, pp. 106:1--106:6, 2016. Google ScholarDigital Library
- S. Venkataramani, et al., "SALSA: Systematic Logic Synthesis of Approximate Circuits," in Proc. DAC, pp. 796--801, 2012. Google ScholarDigital Library
- K. Nepal, et al., "ABACUS: A Technique for Automated Behavioral Synthesis of Approximate Computing Circuits," in Proc. DAC, pp. 1--6, 2014. Google ScholarDigital Library
- C. Li, et al., "Joint Precision Optimization and High Level Synthesis for Approximate Computing," in Proc. DAC, pp. 1--6, 2015. Google ScholarDigital Library
- L. B. Soares, et al., "Approximate Adder Synthesis for Area- and Energy-efficient FIR Filters in CMOS VLSI," in Proc. NEWCAS, pp. 1--4, 2015.Google Scholar
- B. Parhami, Computer Arithmetic: Algorithms and Hardware Designs. New York, NY: Oxford University Press, 2000. Google ScholarDigital Library
- H. R. Mahdiani, et al., "Bio-inspired Imprecise Computational Blocks for Efficient VLSI Implementation of Soft-computing Applications," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 4, pp. 850--862, 2010. Google ScholarDigital Library
- "MARSYAS Data Sets." http://marsyasweb.appspot.com/download/data_sets/.Google Scholar
- G. Tzanetakis and P. Cook, "Musical Genre Classification of Audio Signals," IEEE Speech Audio Process., vol. 10, no. 5, pp. 293--302, 2002.Google ScholarCross Ref
- L. Aksoy, et al., "A Tutorial on Multiplierless Design of FIR Filters: Algorithms and Architectures," Circuits, Systems, and Signal Processing, vol. 33, no. 6, pp. 1689--1719, 2014. Google ScholarDigital Library
- A. V. Oppenheim and A. S. Willsky, Signals and Systems. New Jersey, NJ: Prentice-Hall, 1997. Google ScholarDigital Library
Recommendations
Analog Circuit Fault Simulation Based on Saber
ICCIS '10: Proceedings of the 2010 International Conference on Computational and Information SciencesAlthough analog circuit simulation tool like Saber software are numerous, however, it is lack of software which can simulate analog circuits affected by fault modes. Research in the fields of analog circuit fault simulation has not achieved the same ...
A New Integrated Failure Model for Analog Circuit Simulation Based on Saber
ICEICE '12: Proceedings of the 2012 Second International Conference on Electric Information and Control Engineering - Volume 04A new failure model is proposed to simulate familiar failure mode of analog circuit, such as open-circuit and short-circuit mode. With this new model, it becomes much easier and more convenient to carry out fault injection and fault simulation in analog ...
KaratSaber: New Speed Records for Saber Polynomial Multiplication Using Efficient Karatsuba FPGA Architecture
SABER is a round 3 candidate in the NIST Post-Quantum Cryptography Standardization process. Polynomial convolution is one of the most computationally intensive operation in Saber Key Encapsulation Mechanism, that can be performed through widely explored ...
Comments