Abstract
In this paper we present sim-async, an architectural simulator able to model a 64-bit asynchronous superscalar microarchitecture. The aim of this tool is to serve the designers on the study of different architectural proposals for asynchronous processors. Sim-async models the data-dependant timing of the processor modules by using distribution functions that describe the probability of a given delay to be spent on a computation. This idea of characterizing the timing of the modules at the architectural level of abstraction using distribution functions is introduced for the first time with this work. In addition, sim-async models the delays of all the relevant hardware involved in the asynchronous communication between stages.
To tackle the development of sim-async we have modified the source code of SimpleScalar by substituting the simulator’s core with our own execution engine, which provides the functionality of a parameterizable microarchitecture adapted to the Alpha ISA. The correctness of sim-async was checked by comparing the outputs of the SPEC2000 benchmarks with SimpleScalar executions, and the asynchronous behavior was successfully tested in relation to a synchronous configuration of sim-async.
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References
Kearney, D.: Theoretical Limits on the Data Dependent Performance on Asynchronous Circuits. In: Proc. of Intl. Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 201–207 (1999)
Martin, A.J., Lines, A., Manohar, R., Nystroem, M., Penzes, P., Southworth, R., Cummings, U.: The Design of an Asynchronous MIPS R3000 Microprocessor. In: Adv. Research in VLSI, pp. 164–181 (1997)
Arvind, D.K., Mullins, R.D.: A Fully Asynchronous Superscalar Architecture. In: Proc. of the 1999 Intl. Conf. on Parallel Architectures and Compilation Techniques, pp. 17–22. I. C. S. Press (1999)
Garside, J.D., Bainbridge, W.J., Bardsley, A., Clark, D.M., Edwards, D.A., Furber, S.B., Liu, J., Lloyd, D.W., Mohammadi, S., Pepper, J.S., Petlin, O., Temple, S., Woods, J.V.: AMULET3i - An Asynchronous System-on-Chip. In: Proc. of the 6th Intl. Symposium on Advanced Research in Asynchronous Circuits and Systems, April 2000, pp. 162–175. I. C. S. Press (2000)
Zhang, Q., Theodoropoulos, G.: Modelling SAMIPS: a Synthesisable Asynchronous MIPS Processor. In: Proc. of the 37th Annual Simulation Symposium, April 2004, pp. 205–212 (2004)
Chien, C., Franklin, M.A., Pan, T., Prabhu, P.: ARAS: Asynchronous RISC Architecture Simulator. In: Proc. of the 2nd Working Conference on Asynchronous Design Methodologies (ASYNC 1995) (1995)
Rebello, V.: On the Distribution of Control in Asynchronous Processor Architectures. PhD thesis (1997)
Austin, T.M., Larson, E., Ernst, D.: SimpleScalar: An Infrastructure for Computer System Modeling. IEEE Computer Journal 35(2) (2002)
Sima, D.: Superscalar Instruction Issue. IEEE Micro 17, 28–39 (1997)
Cheng, F.: Practical Design and Performance Evaluation of Completion Detection Circuits. In: Proc. of the Intl. Conf. on Computer Design, pp. 354–359. I. C. S. Press (1998)
Martin, A.J.: Asynchronous Datapaths and the Design of an Asynchornous Adder. Formal Methods in System Design 1, 119–137 (1992)
Meng, T.H.-Y., Brodersen, R.W., Messerschmitt, D.G.: Asynchronous Design for Programmable Digital Signal Processors. IEEE Trans. on Signal Processing 39(4), 939–952 (1991)
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Colmenar, J.M., Garnica, O., Lanchares, J., Hidalgo, J.I., Miñana, G., Lopez, S. (2006). Sim-async: An Architectural Simulator for Asynchronous Processor Modeling Using Distribution Functions. In: Nagel, W.E., Walter, W.V., Lehner, W. (eds) Euro-Par 2006 Parallel Processing. Euro-Par 2006. Lecture Notes in Computer Science, vol 4128. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11823285_51
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DOI: https://doi.org/10.1007/11823285_51
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