ABSTRACT
The simulation speedup of designed RTL NoC regarding the packet transmission is essential to analyze the performance or to optimize NoC parameters for various combinations of intellectual-property (IP) blocks, which requires repeated computations for parameter-space exploration. In this paper, we propose a high-level modeling and simulation (M&S) approach using a revised cellular automata (CA) concept to speed up simulation of dynamic flit movements and queue occupancy within target RTL NoC. The CA abstracts the detailed RTL operations with the view of deciding a cell's state of actions (related to moving packet flits and changing the connection between CA cells) using its own high-level states and those of neighbors, and executing relevant operations to the decided action states. During the performing the operations including connection requests and acceptances, architecture-independent and user-developed routing and arbitration functions are utilized. The decision regarding the action states follows a rule set, which is generated by the proposed test environment. The proposed method was applied to an open-source Verilog NoC, which achieves simulation speedup by approximately 8 to 31 times for a given parameter set.
- A. E. Kiasari, Z. Lu, and A. Jantsch, "An Analytical Latency Model for Networks-on-Chip," IEEE Trans. on Very Large Scale (VLSI) Syst., vol. 21, pp. 113--123, 2013. Google ScholarDigital Library
- E. Fischer and G. P. Fettweis, "An Accurate and Scalable Analytic Model for Round-Robin Arbitration in Network-on-Chip," in NoCS, 2013.Google Scholar
- A. Portero, R. Pla and J. Carrabina, "SystemC Implementation of a NoC," in ICIT, 2005.Google Scholar
- M. Briere et al., "System Level Assessment of an Optical NoC in an MPSoC Platform," in DATE, 2007. Google ScholarDigital Library
- T. Toffoli, "Cellular Automata Machines," Cambridge, MA: The MIT Press, 1987. Google ScholarDigital Library
- M. K. Papamichael and J. C. Hoe, "CONNECT: Re-examining conventional wisdom for designing NoCs in the context of FPGAs," in FPGA, 2012. Google ScholarDigital Library
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