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Reliable Circuit Techniques for Low-Voltage Analog Design in Deep Submicron Standard CMOS: A Tutorial

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Abstract

We present in this paper an overview of circuit techniques dedicated to design reliable low-voltage (1-V and below) analog functions in deep submicron standard CMOS processes. The challenges of designing such low-voltage and reliable analog building blocks are addressed both at circuit and physical layout levels. State-of-the-art circuit topologies and techniques (input level shifting, bulk and current driven, DTMOS), used to build main analog modules (operational amplifier, analog CMOS switches) are covered with the implementation of MOS capacitors.

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References

  1. K. Bult, “Analog design in deep sub-micron CMOS,” in Proc. European Solid-State Conf, 2001.

  2. J. Crols and M. Steyart, “Switched-opamp: An approach to realize full CMOS switched-capacitor circuits at very low power supply voltages.” IEEE J. Solid-State Circuits, vol. 29, no. 8, pp. 936–942, 1994.

    Google Scholar 

  3. V.S.L. Cheung, H.C. Luong, and W.-H. Ki, “A 1-V 10.7-MHz switched-opamp bandpass ΔΣ modulator using double-sampling finite-gain-compensation technique.” IEEE J. Solid-State Circuits, vol. 37, no. 10, pp. 1215–1225, 2002.

    Google Scholar 

  4. J. Sauerbrey et al., “A 0.7-V MOSFET-only switched-opamp ΣΔ modulator in standard digital CMOS technology.” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1662–1669, 2002.

    Google Scholar 

  5. A. Bachirotto and R. Castello, “A1-V 1.8 MHz CMOS switched-opamp SC filter with rail-to-rail output swing.” IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 1979–1986, 1997.

    Google Scholar 

  6. A. Bachirotto, R. Castello, and G.P. Montagna, “Active-series switch for switched-opamp circuit.” Electronics Letters, vol. 34, no. 14, pp. 1365–1366, 1998.

    Google Scholar 

  7. V. Peluso et al., “A 900-mV low-power ΔΣ A/D converter with 77-dB dynamic range.” IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 1887–1897, 1998.

    Google Scholar 

  8. M. Waltari and K.A.I. Halonen, “1-V 9-Bit pipelined switched-opamp ADC.” IEEE J. Solid-State Circuits, vol. 36, no. 1, pp. 129–134, 2001.

    Google Scholar 

  9. V.S.-L. Cheung et al., “A1-V CMOS switched-opamp switched-capacitor pseudo-2-path filter.” IEEE J. Solid-State Circuts, vol. 36, no. 1, pp. 14–22, 2001.

    Google Scholar 

  10. G. Ferri, W. Sansen, and V. Peluso, “A low-voltage fully differential constant-gm rail-to-rail operational amplifier.” Analog Integrated Circuits and Signal Processing, vol. 16, pp. 5–15, 1998.

    Google Scholar 

  11. C.J.-B. Fayomi, M. Sawan, and G.W. Roberts, “A design strategy for a 1-V rail-to-rail input/output CMOS opamp,” in IEEE Proc. International Symposium on Circuits and Systems, Sydney (Australia), May 2001, vol. 1, pp. 639–642.

    Google Scholar 

  12. C.J.-B. Fayomi, G.W. Roberts, and M. Sawan, “Low-voltage CMOS analog switch for high precision sample-and-hold circuit.” 43rd Midwest Symposium on Circuits and Systems, East Lansing, Aug. 2000.

  13. S. Karthikeyan et al., “Low-voltage analog circuit design based on biased inverting opamp configuration.” IEEE Trans. Circuits and Systems II, vol. 47, no. 3, pp. 176–184, 2000.

    Google Scholar 

  14. E.K.F. Lee, “Low-voltage opamp design and differential difference amplifier design using linear transconductor with resistor input.” IEEE Trans. Circuits and Systems II, vol. 47, no. 7, pp. 776–778, 2000.

    Google Scholar 

  15. J. Ramirez-Angulo et al., “Low-voltage CMOS op-amp with wide input-output swing based on a novel scheme.” IEEE Trans. Circuits and Systems I, vol. 47, no. 5, pp. 772–774, 2000.

    Google Scholar 

  16. J. Ramirez-Angulo et al., “Low-voltage CMOS op-amp with rail-to-rail input and output signal swing for continuous-time signal processing using multiple-input floating-gate transistors.” IEEE Trans. Circuits and Systems II, vol. 48, no. 1, pp. 111–116, 2001.

    Google Scholar 

  17. J. Fonderie et al., “1-V operational amplifier with rail-to-rail input and output stages.” IEEE J. Solid-State Circuits, vol. 24, no. 12, pp. 1551–1559, 1989.

    Google Scholar 

  18. J.F. Duque-Carillo et al., “1-V rail-to-rail operational amplifies in standard CMOS technology.” IEEE J. Solid-State Circuits, vol. 35, no. 1, pp. 33–44, 2000.

    Google Scholar 

  19. A. Guzinski, M. Bialko, and J.C. Matheau, “Body-driven differential amplifier for application in continuous-time active-C filter,” in Proc. European Conf. Circuit Theory and Design (ECCTD'87), 1987, pp. 315–320.

  20. B.J. Blalock, P.E. Allen, and G.A. Rincon-Mora, “Designing 1-V opamp using standard digital CMOS technology.” IEEE Trans. Circuits and Systems II, vol. 45, no. 7, pp. 930–936, 1998.

    Google Scholar 

  21. T. Lehmann and M. Cassia, “1-V power supply CMOS cascode amplifier.” IEEE J. Solid-State Circuits, vol. 36, no. 7, pp. 1082–1086, 2001.

    Google Scholar 

  22. T.A.F. Duisters and E.C. Dijkmans, “A-90 dB THD Rail-to-rail input opamp using a new local charge pump in CMOS.” IEEE J. Solid-State Circuits, vol. 33, no. 7, pp. 947–955, 1998.

    Google Scholar 

  23. S.A. Jackson, J.C. Killens, and B.J. Blalock, “A programmable current mirror for analog trimming using single-poly floatinggate devices in standard CMOS technology.” IEEE Trans. Circuits Systems II, vol. 48, no. 1, pp. 100–102, 2001.

    Google Scholar 

  24. L.S.Y. Wong et al., “A 1-V CMOS D/A converter with multiinput floating-gate MOSFET.” IEEE J. Solid-State Circuits, vol. 34, no. 10, pp. 1386–1390, 1999.

    Google Scholar 

  25. R.G Carvajal et al., “Low-power low-voltage differential class-AB OTA's for SC circuits.” Electronics Letters, vol. 38, no. 2, pp. 1304–1305, 2002.

    Google Scholar 

  26. W. Aloisi, G. Giustoli, and G. Palumbo, “1 V CMOS output stage with excellent linearity.” Electronics Letters, vol. 38, no. 2, pp. 1299–1300, 2002.

    Google Scholar 

  27. G. Palmisano, G. Palumbo, and R. Salerno, “CMOS output stages for low-voltage power supply.” IEEE Trans Circuits Systems II, vol. 47, no. 2, pp. 96–104, 2000.

    Google Scholar 

  28. A. Srivastava, “Back-gate bias method of threshold voltage control for the design of low-voltage CMOS ternary logic circuits.” Microelectronics Reliability, vol. 40, no. 12, pp. 2107–2110, 2000.

    Google Scholar 

  29. A.-J. Annema, “Low-power bandgap references featuring DTMOST's.” IEEE J. Solid-State Circuits, vol. 34, no. 7, pp. 949–955, 1999.

    Google Scholar 

  30. F. Assaderaghi et al., “A dynamic threshold voltage MOSFET (DTMOST) for ultra low-voltage operation,” in Proc. IEDM'94, 1994, pp. 809–812.

  31. M.J.M. Pelgrom et al., “Matching properties of MOS transistors.” IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1433–1440, 1989.

    Google Scholar 

  32. P. Mandal and V. Visvanatha, “CMOS op-amp sizing using a geometric programming formulation.” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 1, pp. 22–38, 2001.

    Google Scholar 

  33. T. Brooks et al., “A cascade sigma-delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR.” IEEE J. Solid State Circuits, vol. 32, no. 12, pp. 1896–1906, 1997.

    Google Scholar 

  34. S.R. Norsworthy, R. Schreier, and G.C. Temes, Delta-Sigma Data Converters: Theory, Design and Simulation. IEEE Press, Chapter 11 (Section 11-3), 1996.

  35. J. Steengaard-Madsen, “Bootstrapped low-voltage switch.” US Patent 6 215 348, April 10th, 2001.

  36. A.M. Abo and P.R. Gray, “A 1.5-V, 10-bit, 14 MS/s CMOS pipeline analog-to-digital converter.” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599–605, 1999.

    Google Scholar 

  37. M. Dessoury and A. Kaiser, “Very low-voltage digital-audio ΔΣmodulator with 88-dB dynamic range using local switch bootstrapping.” IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 349–355, 2001.

    Google Scholar 

  38. L. Singer and T.L. Brooks, “Two-phase bootstrapped CMOS switch drive technique and circuit,” US Patent 6 060 937, May 9th, 2000.

  39. L. Singer and T.L. Brooks, “Two-phase bootstrapped CMOS switch drive technique and circuit,” US Patent 6 118 326, Sept. 12th, 2000.

  40. J.L. Bledsoe, “Bootstrapped CMOS sample and hold circuitry and method,” US Patent 6 072 355, June 6th, 2000.

  41. J.N. Burghartz et al., “Integrated RF components in a SiGe bipolar technology.” IEEE J. Solid-State Circuits, vol. 32, no. 9, pp. 1440–1445, 1997.

    Google Scholar 

  42. H. Samavati et al., “Fractal capacitors.” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2035–2041, 1998.

    Google Scholar 

  43. O.E. Akcasu, “High capacitance structure in a semiconductor device,” US Patent 5 208 725, May 4th, 1993.

  44. D.I. Hariton, “Floating MOS capacitor,” US Patent 5 926 064, July 20th, 1999.

  45. T. Tille et al., “A 1.8-V MOSFET-only ΔΣ modulator using substrate biased depletion-mode MOS capacitors in series compensation.” IEEE J. Solid-State Circuits, vol. 36, no. 7, pp. 1041–1047, 2001.

    Google Scholar 

  46. J.M. Rabey, Digital Integrated Circuits: A Design Perpective. Prentice Hall: New Jersey, Chapter 8, 1996.

    Google Scholar 

  47. R. Aparicio and A. Hajimiri, “Capacity limits and matching properties of integrated capacitors.” IEEE J. Solid-State Circuits, vol. 37, no. 3, pp. 384–393, 2002.

    Google Scholar 

  48. M. McNutt and R. Hershbarger, “Layout scheme for precise capacitor ratios,” US Patent 5 322 438, June 21th, 1994.

  49. F. Maloberti, “Layout of analog and mixed analog-digital circuits,” in Design of Analog-Digital VLSI Circuits for Telecommunications and Signal Processing, 2nd editor, Prentice Hall: New Jersey, Chapter 11, 1994.

    Google Scholar 

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Authors and Affiliations

  1. Department of Electrical Engineering, Ecole Polytechnique de Montreal, Montreal, (QC), Canada

    Christian Jésus B. Fayomi & Mohamad Sawan

  2. Department of Electrical Engineering, McGill University, Canada

    Gordon W. Roberts

Authors
  1. Christian Jésus B. Fayomi
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  2. Mohamad Sawan
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  3. Gordon W. Roberts
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Fayomi, C.J.B., Sawan, M. & Roberts, G.W. Reliable Circuit Techniques for Low-Voltage Analog Design in Deep Submicron Standard CMOS: A Tutorial. Analog Integrated Circuits and Signal Processing 39, 21–38 (2004). https://doi.org/10.1023/B:ALOG.0000016641.83563.96

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  • DOI: https://doi.org/10.1023/B:ALOG.0000016641.83563.96

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