Design method for CMOS current-source modes power amplifiers based on PAE optimization

Abstract

An efficient method for CMOS current-source modes (A, B, AB, C classes) Power Amplifier (PA) design for low-power applications is presented. This method allows to set the conduction angle α and the transistor size W/L in order to maximize the PAE. In a first step, an analytical approach, built from a simple transistor model, gives a first approximation of the optimum α and W/L. In a second step and from the analytical results, a simulation approach, illustrated with a 0.28μm CMOS foundry design-kit, allows to precisely determine the optimum conduction angle and the transistor size. A PA designed with this method at 2.45 GHz for a class 2 Bluetooth application shows a 41% PAE and a surface consumption of 0.28 mm² for an output power of 4 dBm.