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A design of EPIC type processor based on MIPS architecture

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Abstract

This paper proposes an EPIC (Explicitly Parallel Instruction Computing Architecture) type processor based on MIPS. VLIW processors can execute multiple instructions simultaneously, but due to dependency of instructions, it is often impossible to execute maximum parallel execution. As a result, program contains many NOP instructions. EPIC processor can reduce NOP instructions by changing number of instructions to be executed simultaneously. To implement EPIC type processor, five bit field is embedded in the machine instruction code. For comparison, a 5-stage pipeline processor (basic processor), and a Very Long Instruction Word (VLIW) processor are designed. The proposed processors are described in hardware description language (VHDL) and implemented using FPGA. Operations are confirmed by software Tera Term. Processors are evaluated for instruction parallelism and program size using bubble sort program. It is confirmed that the proposed processor is 1.9 times faster than the basic processor. In addition, the program size of the proposed processor is 64 bytes, the basic processor is 56 bytes, and the VLIW processor is 80 bytes.

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Authors and Affiliations

  1. Tokyo Denki University, Tokyo, Japan

    Takahito Hayashi & Akinori Kanasugi

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  1. Takahito Hayashi
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  2. Akinori Kanasugi
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Correspondence to Takahito Hayashi.

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This work was presented in part at the 24th International Symposium on Artificial Life and Robotics (Beppu, Oita, January 23–25, 2019).

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Hayashi, T., Kanasugi, A. A design of EPIC type processor based on MIPS architecture. Artif Life Robotics 25, 59–63 (2020). https://doi.org/10.1007/s10015-019-00554-w

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