Abstract
This paper demonstrates the integration of fully depleted ultra thin-body Silicon on Insulator MOSFET (FD UTB SOI n and p-MOSFET) into CMOS inverter circuit. The proposed MOS device shows the better Ion to Ioff ratio, lower subthreshold slope and low threshold voltage at 50 nm gate length. The proposed CMOS circuit shows the good inverter VTC curve, and minimum delay has been obtained at 50 nm gate length. The proposed structures were designed and simulated using Sentaurus device simulator.
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Acknowledgments
This work is supported by the AICTE under research promotion scheme (RPS-60). Authors would also like to thank incubation cell of IIT Kanpur to provide Sentaurus tool in VLSI/EDA lab.
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Mishra, V.K., Chauhan, R.K. (2016). Performance Analysis of Fully Depleted Ultra Thin-Body (FD UTB) SOI MOSFET Based CMOS Inverter Circuit for Low Power Digital Applications. In: Satapathy, S.C., Mandal, J.K., Udgata, S.K., Bhateja, V. (eds) Information Systems Design and Intelligent Applications. Advances in Intelligent Systems and Computing, vol 434. Springer, New Delhi. https://doi.org/10.1007/978-81-322-2752-6_37
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DOI: https://doi.org/10.1007/978-81-322-2752-6_37
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