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Performance Analysis of Fully Depleted Ultra Thin-Body (FD UTB) SOI MOSFET Based CMOS Inverter Circuit for Low Power Digital Applications

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Information Systems Design and Intelligent Applications

Part of the book series: Advances in Intelligent Systems and Computing ((AISC,volume 434))

Abstract

This paper demonstrates the integration of fully depleted ultra thin-body Silicon on Insulator MOSFET (FD UTB SOI n and p-MOSFET) into CMOS inverter circuit. The proposed MOS device shows the better Ion to Ioff ratio, lower subthreshold slope and low threshold voltage at 50 nm gate length. The proposed CMOS circuit shows the good inverter VTC curve, and minimum delay has been obtained at 50 nm gate length. The proposed structures were designed and simulated using Sentaurus device simulator.

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References

  1. J. Chen, J. Luo, Q. Wu, Z. Chai, T. Yu, Y. Dong, and X. Wang, A Tunnel Diode Body Contact Structure to Suppress the Floating-Body Effect in Partially Depleted SOI MOSFETs, IET, Electron Device Lett., vol. 32 no. 10, pp. 1346–1348, Oct. 2011.

    Google Scholar 

  2. Y. Wang, X.-W. He, and C. Shan, A Simulation Study of SoI-Like Bulk Silicon MOSFET With Improved Performance, IEEE Trans. Electron Devices, vol. 61 no. 9, pp. 3339–3344, Sept. 2014.

    Google Scholar 

  3. A. Ohata, Y. Bae, C. Fenouillet-Beranger, and S. Cristoloveanu, Mobility Enhancement by Back-Gate Biasing in Ultrathin SOI MOSFETs With Thin BOX, IEEE Electron Device Lett., vol. 33, no. 3, pp. 348–350, March. 2012.

    Google Scholar 

  4. M. Miura-mattausch, U. Feldmann, Y. Fukunaga, M. Miyake, H. Kikuchihara, F. Ueno, H. J. Mattausch, S. Member, and I. Paper, Compact Modeling of SOI MOSFETs With Ultrathin Silicon and BOX Layers, IEEE Trans. Electron Devices, vol. 61, no. 2, pp. 255–265, Feb. 2014.

    Google Scholar 

  5. J. Luo, J. Chen, Q. Wu, Z. Chai, T. Yu, and X. Wang, TDBC SOI technology to suppress floating body effect in PD SOI p-MOSFETs, IEEE Electronics Lett., vol. 48, no. 11, pp. 652–653, May. 2012.

    Google Scholar 

  6. V. P. Trivedi, S. Member, and J. G. Fossum, Scaling Fully Depleted SOI CMOS, IEEE Trans. Electron Devices vol. 50 no. 10, pp. 2095–2103, Oct. 2003.

    Google Scholar 

  7. S. Zhang, R. Han, X. Lin, X. Wu, and M. Chan, A Stacked CMOS Technology on SOI Substrate, IEEE Electron Device Lett., vol. 25 no. 9 pp. 661–663, Sept. 2004.

    Google Scholar 

  8. J. B. Kuo, W. C. Lee, and J. Sim, Back-Gate Bias Effect on the Subthreshold Behavior and the Switching Performance in an Ultrathin SO1 CMOS Inverter Operating at 77 and 300 K IEEE Transactions on Electron Devices, vol. 39, no. 12, pp. 2781–2790, Dec 1992.

    Google Scholar 

  9. S. M. Sze. Physics of Semiconductor Devices, 2nd edition.. New York: John Wiley & Sons, 1981.

    Google Scholar 

  10. Sentaurus Device User Guide,Mountain View, CA: Synopsys, Inc., 2010.

    Google Scholar 

  11. J. Singh and C. Sahu, Device and circuit performance analysis of double gate junctionless transistors at Lg = 18 nm, pp. 1–6, Feb. 2014.

    Google Scholar 

  12. Y. Khatami and K. Banerjee, Steep Subthreshold Slope n- and p-Type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits, IEEE Trans. Electron Devices, vol. 56, no. 11, pp. 2752–2761, Nov. 2009.

    Google Scholar 

  13. V. Nagavarapu, S. Member, R. Jhaveri, and J. C. S. Woo, The Tunnel Source (PNPN) n-MOSFET : A Novel High Performance Transistor, IEEE Transactions on Electron Devices, vol.55, no. 4, pp. 1013–1019, April 2008.

    Google Scholar 

  14. H. Zhongfang, Ru. Guoping, and R. Gang, Analysis of The Subthreshold Characteristics of Vertical Tunneling Field Effect Transistors, Journal of Semiconductors, Vol. 34, no. 1, pp. 1–7, Jan. 2013.

    Google Scholar 

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Acknowledgments

This work is supported by the AICTE under research promotion scheme (RPS-60). Authors would also like to thank incubation cell of IIT Kanpur to provide Sentaurus tool in VLSI/EDA lab.

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Correspondence to Vimal Kumar Mishra .

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Mishra, V.K., Chauhan, R.K. (2016). Performance Analysis of Fully Depleted Ultra Thin-Body (FD UTB) SOI MOSFET Based CMOS Inverter Circuit for Low Power Digital Applications. In: Satapathy, S.C., Mandal, J.K., Udgata, S.K., Bhateja, V. (eds) Information Systems Design and Intelligent Applications. Advances in Intelligent Systems and Computing, vol 434. Springer, New Delhi. https://doi.org/10.1007/978-81-322-2752-6_37

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  • DOI: https://doi.org/10.1007/978-81-322-2752-6_37

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